Stair Step Structures in 3D Memory Arrays
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Solution Overview
Problem
Conventional vertical memory arrays face challenges in increasing memory density and reducing manufacturing costs, with stair step structures requiring additional lateral width for more conductive tiers and access lines, leading to electrical stress and increased complexity.
Innovation Solution
The semiconductor device structure incorporates stair step structures positioned between longitudinal ends and lateral side surfaces of the memory array block, allowing for a greater number of conductive tiers without increasing lateral width, and spacing access lines further to reduce electrical stress and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stair step structures are used to increase the number of conductive tiers, then memory density is improved, but lateral width increases
Solution Approach 1:
The patent repositions stair step structures from lateral extensions to vertical integrations within the memory array block. By placing stair step structures between longitudinal ends rather than extending laterally, the design enables access to multiple conductive tiers through vertical stacking while maintaining constrained lateral dimensions. This dimensional reconfiguration allows increased memory density without proportional increases in lateral width.
2Area of stationary object
If access lines are placed closer together to reduce lateral width, then device area is reduced, but electrical stress increases
Solution Approach 1:
The patent segments the memory array block into distinct regions with stair step structures positioned between longitudinal ends, creating separate access pathways. This segmentation allows access lines to be strategically routed through stair step contact regions, effectively distributing electrical stress across multiple isolated contact points rather than concentrating it in densely packed lateral regions. The segmentation enables reduced device area while maintaining acceptable electrical stress levels through spatial distribution.
3Quantity of substance
If stair step structures extend laterally to accommodate more access lines, then access to more conductive tiers is enabled, but manufacturing complexity increases
Solution Approach 1:
The patent merges the functions of multiple access lines and conductive tier connections into integrated stair step structures. Each stair step structure combines multiple contact regions for different conductive tiers into a single unified formation process. This merging reduces manufacturing complexity by enabling simultaneous formation of multiple contacts through single patterning and etching operations, rather than requiring separate lateral extensions for each access line.
Data Source
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AI summary
Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.