Stair Step Pad Structures for Dense Vertical Memory Routing
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Solution Overview
Problem
Conventional vertical memory arrays face challenges in increasing memory density without increasing the overall width of the stack structure, leading to complex and congested routing paths, which can result in electrical shorting and increased risk of punching through the staircase structure during contact formation.
Innovation Solution
The formation of microelectronic devices with stair step regions featuring vertically alternating conductive and insulative structures, where uppermost stair step structures include isolated nitride structures replaced with conductive pad structures for electrical communication, while the lowermost stair step structures do not, preventing shorting and reducing the risk of punching through.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the quantity of tiers of conductive structures is increased to provide additional memory density, then memory density is improved, but the complexity and congestion of routing paths increases leading to electrical shorting risks
Solution Approach 1:
The patent transitions from planar routing to three-dimensional routing by forming staircase structures with multiple levels. Conductive contact structures are positioned at different vertical heights corresponding to different tiers of conductive structures, allowing electrical connections to be made in the vertical dimension rather than requiring complex lateral routing paths. This dimensional transition reduces routing congestion and prevents electrical shorting while maintaining high memory density.
2Quantity of substance
If the height of the staircase structure is increased to accommodate more tiers, then memory density is improved, but the risk of punching through the uppermost steps during contact formation increases
Solution Approach 1:
The patent performs preliminary formation of the staircase structure with precisely controlled step heights and depths before forming the conductive contact structures. The etching process creates predetermined landing zones at each tier level, ensuring that subsequent contact formation operations can reliably connect to the correct conductive structure without punching through to underlying layers. This preliminary structuring establishes a robust framework that prevents formation defects even as the staircase height increases to accommodate more memory tiers.
3Quantity of substance
If the quantity of steps in individual staircase structures is increased to connect to additional tiers, then memory density is improved, but the likelihood of different electrically conductive portions shorting to each other increases
Solution Approach 1:
The patent segments the staircase structure into distinct levels, with each level containing a specific tier of conductive structures and associated contact regions. The etching process creates isolated steps at different vertical positions, and conductive contact structures are formed independently at each level. This segmentation physically separates different electrical domains, preventing unwanted interactions and shorting between conductive portions at different tiers while enabling connections to multiple memory layers.
Data Source
AI summary
A method of forming a microelectronic device comprises forming isolated nitride structures on steps of stair step structures comprising stacked tiers comprising alternating levels of a first insulative material and a second insulative material, forming a photoresist material over some of the stair step structures, and replacing the isolated nitride structures and the second insulative material with an electrically conductive material to respectively form conductive pad structures and electrically conductive lines. Related microelectronic devices and electronic devices are also disclosed.