Stair Step Structures Using Sacrificial Planarization
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Solution Overview
Problem
Conventional methods for forming stair step structures in vertical memory arrays face challenges in filling insulative materials between adjacent regions, leading to damage of conductive word lines and potential device failure due to excessive chemical mechanical planarization, which thins the uppermost conductive tiers and disrupts electrical connections.
Innovation Solution
The use of sacrificial materials to pattern and planarize insulative materials between stair step regions, ensuring that the uppermost conductive tiers are not thinned during the process, by configuring the chemical mechanical planarization to stop on the sacrificial material, thereby maintaining the integrity of the conductive layers and reducing device failure rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical planarization is used to fill insulative materials between stair step regions, then the regions are effectively filled, but the uppermost conductive tiers are thinned and damaged
Solution Approach 1:
A sacrificial material is deposited over the uppermost conductive tier before the chemical mechanical planarization process. This preliminary action creates a protective layer that prevents the planarization process from thinning or damaging the conductive word lines, while still allowing the insulative material to be properly filled in the stair step regions.
Solution Approach 2:
The sacrificial material acts as an intermediary between the chemical mechanical planarization process and the uppermost conductive tier. It mediates the interaction by absorbing the planarization action, thereby protecting the conductive structure from direct contact with the planarization tools and chemicals.
2Quantity of substance
If the number of memory cells in vertical strings is increased to increase memory density, then memory density is improved, but the depth of the stair step structure increases making insulative material filling difficult
Solution Approach 1:
The sacrificial material is deposited in advance before the insulative material filling process. This preliminary deposition enables the subsequent planarization to proceed uniformly across the entire surface, including deep stair step regions, without causing damage to underlying structures.
Solution Approach 2:
The introduction of the sacrificial material changes the surface topology parameter, creating a uniform starting surface for planarization. This parameter change allows the chemical mechanical planarization process to effectively fill deep stair step regions while maintaining control over the planarization depth.
3Quantity of substance
If conventional stair step formation processes are used with increased number of tiers, then vertical memory array capacity is improved, but damage to conductive structures increases leading to device failure
Solution Approach 1:
The sacrificial material is deposited before any planarization or etching processes that could damage the conductive structures. This preliminary protective layer ensures that even as the number of tiers increases and the stair step depth increases, the conductive word lines remain protected from damage throughout the subsequent manufacturing processes.
Solution Approach 2:
The sacrificial material serves as a cushioning layer that absorbs the mechanical and chemical stress of the planarization process. By providing this beforehand cushioning, the conductive structures are protected from the harmful effects of excessive planarization, even in devices with many tiers and deep stair steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively fills the regions between stair step structures without damaging the uppermost tiers, reducing failure rates and maintaining reliable electrical connections, thus enhancing the stability and performance of semiconductor devices.
Implementation Method 1
chemical mechanical planarization of insulative materials located between adjacent regions of the stair step structure
Data Source
AI summary
A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.