3D Memory Stair-Step Word Lines With Under-Array Peripheral Circuit
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Solution Overview
Problem
Current two-dimensional semiconductor devices face limitations in increasing integration density due to the fineness of micro-pattern formation, which requires specialized equipment and results in incremental gains.
Innovation Solution
A three-dimensional semiconductor memory device is designed with memory cells arranged vertically and a stair-step configuration for the ends of word lines, along with a peripheral circuit that overlaps the connection region, including main and dummy pass transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional planar configuration is used for memory cells, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional vertical arrangement of memory cells. The word lines are configured in a stair-step pattern across multiple levels, with bit lines extending vertically to connect memory cells at different heights. This dimensional change allows significantly higher integration density without requiring finer micro-pattern formation, as the increased storage capacity comes from utilizing the third dimension (vertical stacking) rather than reducing the planar footprint of individual cells.
2Quantity of substance
If fineness of micro-patterns is increased to improve integration density, then more memory cells can be packed, but specialized equipment is required and manufacturing complexity increases
Solution Approach 1:
Instead of increasing micro-pattern fineness in the planar direction, the patent achieves higher integration density by stacking memory cells vertically in three dimensions. The stair-step word line configuration and vertical bit lines allow multiple memory cells to be arranged along the vertical axis, effectively using the third dimension to increase capacity without requiring more complex micro-pattern formation equipment or processes.
Solution Approach 2:
The memory cell array is divided into multiple blocks, with each block containing a set of memory cells arranged in the stair-step configuration. This segmentation allows the complex three-dimensional structure to be managed as repeating modular units, simplifying the manufacturing process by breaking down the overall complex structure into manageable segments that can be fabricated using standard processes.
3Ease of operation
If peripheral circuit is placed separately from memory cell region, then control functionality is achieved, but device area increases
Solution Approach 1:
The patent merges the peripheral circuit region with the memory cell region by placing the peripheral circuit underneath the memory cell array in the vertical direction. The word lines are configured to extend from the peripheral circuit region upward to connect with the memory cells, creating an integrated structure where the peripheral circuit and memory cells occupy overlapping horizontal footprints. This merging significantly reduces the overall device area while maintaining full control functionality, as the peripheral circuit shares the same planar space with the memory cells through vertical stacking.
Data Source
AI summary
A three-dimensional (3D) semiconductor memory device is provided. The device includes: a memory cell region; and a peripheral circuit configured to control the memory cell region. The memory cell region includes: a cell array region including memory cells arranged vertically along a vertical direction; and a connection region including ends of word lines that are connected to the memory cells, wherein the ends form a stair-step configuration. The peripheral circuit includes a peripheral circuit region overlapping the connection region along the vertical direction. The peripheral circuit region includes a first main pass transistor electrically connected to a first word line of the word lines, and a first dummy pass transistor electrically separated from the word lines. The first main pass transistor and the first dummy pass transistor are arranged along a first direction perpendicular to the vertical direction.