3D Memory Staircase Blocks With Cross-Block Via Connections
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Solution Overview
Problem
Conventional 3D memory arrays face challenges in increasing memory density and reducing fabrication costs due to complexities in electrically connecting memory cells to control logic devices, which leads to sizing and spacing issues with routing and interconnect structures.
Innovation Solution
The design incorporates a microelectronic device with a base structure and memory structure featuring stadium structures, conductive contact structures, and conductively filled vias, allowing for efficient electrical connections between memory cells and string driver circuitry through alternating staircase structures and vias, optimizing the arrangement of conductive and insulative tiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 3D memory arrays use traditional routing and interconnect structures to electrically connect memory cells to control logic devices, then memory density can be increased, but sizing and spacing complications arise due to increased quantities and dimensions of routing structures
Solution Approach 1:
The patent divides the memory array into multiple blocks, each containing a subset of memory cells. Control logic devices are distributed across these blocks rather than centralized, segmenting the routing requirements. This segmentation reduces the complexity of interconnect structures by localizing connections within each block, while still achieving high overall memory density through the multi-block architecture.
Solution Approach 2:
The patent transitions from planar 2D routing to three-dimensional routing structures that extend vertically through the memory array. By utilizing the vertical dimension for interconnect pathways, the design reduces lateral spacing requirements and simplifies routing complexity while maintaining high memory density through vertical stacking of memory cells and control logic.
2Quantity of substance
If the number of memory cells in a 3D memory array is increased, then memory density improves, but electrically connecting these memory cells to control logic devices creates sizing and spacing complications
Solution Approach 1:
The patent implements a nested hierarchical structure where memory cells are organized into strings, strings are grouped into blocks, and blocks are arranged in tiers. Control logic devices are nested within specific blocks rather than requiring connections to all memory cells directly. This nested organization allows scaling to large numbers of memory cells while maintaining manageable connection complexities and standardized spacing requirements at each hierarchical level.
3Reliability
If conventional routing structures are used to facilitate electrical connections in 3D memory arrays, then memory cells can be connected to control logic, but the quantities, dimensions, and arrangements of control logic devices impede reductions to array size and increases to storage density
Solution Approach 1:
The patent merges control logic devices with memory cell arrays by integrating control logic within the same three-dimensional space as the memory cells, rather than separating them into distinct planar layers. This merging allows control logic to share vertical space with memory structures, reducing the overall footprint area while maintaining reliable electrical connections through integrated routing pathways that serve both memory and control functions.
Data Source
AI summary
A microelectronic device comprises blocks, contact structures, filled vias, and a base structure. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each block comprises a forward staircase structure and a reverse staircase structure. The contact structures are on steps of the forward staircase structure of a first of the blocks and on additional steps of the reverse staircase structure of a second of the blocks horizontally neighboring the first of the blocks. The filled vias extend through portions of the first of the blocks within horizontal boundaries of the reverse staircase structure of the first of the blocks and extend through portions of the second of the blocks within horizontal boundaries of the forward staircase structure of the second of the blocks. The base structure underlies the blocks and comprises transistors coupled to the filled vias.