Staircase Code Decoding for Small-Block Storage Error Correction
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Solution Overview
Problem
Traditional staircase codes require large code words arranged in multiple large blocks for effective error correction, which is inefficient for applications like storage systems that handle smaller data sectors, wasting processing and power resources.
Innovation Solution
Implementing a staircase code error correction scheme with small block sizes, using an outer BCH code to compensate for increased error likelihood, and decoding methods that span multiple rows and columns to maintain correction capabilities without impractical block sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional staircase codes use large code words arranged in multiple large blocks, then error correction capability is improved, but processing efficiency and power consumption deteriorate for storage systems handling smaller data sectors
Solution Approach 1:
The patent divides the traditional large staircase code into multiple smaller staircase codes, each processing a smaller data sector. This segmentation allows storage systems to decode only the necessary small blocks rather than processing entire large code words, significantly improving processing efficiency while maintaining error correction capability for each segment
Solution Approach 2:
The patent changes the block size parameter from large traditional blocks to small blocks optimized for storage sector sizes. By adjusting this fundamental parameter, the system achieves better alignment with storage system requirements, reducing processing overhead and power consumption while maintaining adequate error correction through the layered coding approach
2Productivity
If small block sizes are used in staircase codes, then processing efficiency is improved, but error correction capability deteriorates
Solution Approach 1:
The patent implements a nested coding structure where an outer BCH code layer is applied to the data before encoding with the inner staircase code. This nested approach allows small block sizes in the staircase code to maintain processing efficiency while the outer BCH layer provides enhanced error correction capability, compensating for the reduced block size
Solution Approach 2:
The patent creates a composite error correction scheme by combining two different coding approaches: BCH code for the outer layer and staircase code for the inner layer. This composite structure leverages the strengths of both codes - BCH provides robust error correction for small blocks while staircase code enables efficient processing through its iterative decoding approach
3Reliability
If large blocks are used for staircase code encoding, then error correction capability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent segments the large block processing into multiple small block operations. Each small block can be decoded independently or in small groups, reducing the complexity of any single processing operation and lowering power consumption while maintaining overall error correction capability across the segmented structure
Data Source
AI summary
An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a plurality of columns and further configured to compute a first syndrome for at least a portion of a first component codeword of the codeword. The apparatus further comprises a second syndrome computation circuit configured to receive the codeword and to compute a second syndrome for at least a portion of a second component codeword of the codeword. The apparatus further comprises a bit correction circuit configured to correct one or more erroneous bits in the codeword based, at least in part, on at least one of the first and second syndrome, wherein the first and second component codewords span two or more rows and two or more columns of the codeword.