Staircase Conductive Structures for High-Density DRAM Interconnects
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Solution Overview
Problem
The increased density of memory cells in microelectronic devices leads to difficulties in forming conductive interconnect structures that can adequately communicate with the memory cells, and the area occupied by these interconnects increases, complicating the design and fabrication of compact and efficient memory devices.
Innovation Solution
A microelectronic device design that incorporates a staircase structure horizontally neighboring a memory array region, with vertically stacked memory cells. The staircase structure includes vertically spaced conductive structures that horizontally extend through the array region and are shared between adjacent memory cell stacks, facilitating electrical communication and reducing the horizontal area occupied by the staircase structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of memory cells is increased, then the integration level and compactness are improved, but the difficulty of forming conductive interconnect structures increases and the area occupied by interconnects increases
Solution Approach 1:
The patent transitions from two-dimensional planar interconnect structures to three-dimensional vertically stacked conductive structures. The conductive interconnect structures extend vertically through multiple memory cell decks, enabling electrical communication across multiple levels without increasing horizontal footprint. This dimensional change resolves the contradiction by maintaining high memory cell density while simplifying interconnect formation through vertical stacking rather than complex horizontal routing.
Solution Approach 2:
The conductive interconnect structures serve multiple functions simultaneously: they provide electrical communication for multiple memory cell decks, act as shared interconnects for vertically stacked memory cells, and reduce the overall interconnect area. By making the interconnect structures multi-functional, the patent reduces device complexity while maintaining high memory cell density.
2Quantity of substance
If the spacing between neighboring conductive interconnect structures is decreased, then the memory cell density is improved, but the reliability of forming adequate conductive interconnect structures deteriorates
Solution Approach 1:
The patent moves interconnect spacing requirements from the horizontal plane to the vertical dimension. By stacking conductive interconnect structures vertically, the design achieves high memory cell density with adequate spacing maintained in the vertical direction, improving reliability of interconnect formation while maintaining high density.
3Adaptability or versatility
If the area occupied by electrical interconnects is increased, then the connectivity between memory cells is improved, but the compactness and integration level of the device deteriorates
Solution Approach 1:
The patent utilizes the vertical dimension to provide extensive connectivity between memory cells without increasing horizontal area. Conductive interconnect structures extend vertically to connect multiple decks and memory cells, achieving high adaptability and connectivity while maintaining compact horizontal footprint.
Solution Approach 2:
The conductive interconnect structures are nested vertically within the memory device architecture, with interconnects for multiple decks stacked one above another. This nesting approach provides comprehensive connectivity between all memory cells while occupying minimal horizontal space, resolving the contradiction between connectivity and compactness.
Data Source
AI summary
A microelectronic device comprises a memory array region comprising vertical stacks of dynamic random access memory (DRAM) cells, each of the DRAM cells comprising a storage device of a vertical stack of storage devices and a horizontally neighboring access device of a vertical stack of access devices, and a staircase region substantially horizontally neighboring the memory array region in a first horizontal direction. The staircase region comprises a vertical stack of first conductive structures horizontally extending through the staircase region in the first horizontal direction, the first conductive structures in contact with the first DRAM cells and the second DRAM cells, and sub-staircase structures individually comprising second conductive structures in contact with the first conductive structures and horizontally extending from the first conductive structures in a second horizontal direction substantially perpendicular to the first horizontal direction, each of the sub-staircase structures individually comprising at least four steps, each step defined at horizontal boundaries of the second conductive structure defining the step. Related memory devices and electronic systems are also described.