Staircase Conductive Line Contacts for Dense 3D DRAM Interconnects

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Solution Overview

Problem

Conventional memory devices face challenges in increasing interconnection density due to traditional conductive line geometries, which result in larger interconnection areas and difficulties in coupling conductive lines to sense amplifiers or word line drivers in 3D DRAM arrays.

Innovation Solution

The implementation of multi-direction conductive lines and staircase conductive line contact structures allows for more efficient interconnection by forming horizontal access devices with vertically oriented access lines and digit lines, reducing spatial constraints and enabling denser connections between conductive lines and sense amplifiers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional conductive line geometries are used, then the interconnection structure is simple to manufacture, but the interconnection density is low and spatial occupancy is large

Engineering Contradiction:
Improveinterconnection densityVSAvoidinterconnection area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent transitions from planar 2D conductive line geometries to 3D multi-directional conductive line structures with staircase contact regions. Conductive lines are extended in multiple directions (first direction, second direction, third direction) and stacked vertically across multiple tiers, utilizing the third dimension to increase interconnection density without proportionally increasing the planar footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The staircase conductive line contact structure implements a nested arrangement where conductive lines from different tiers are vertically stacked and interconnected. Lower-tier conductive lines are positioned beneath upper-tier conductive lines, creating a nested 3D configuration that maximizes space utilization and increases the number of interconnections within a compact volume.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If multi-direction conductive lines and staircase contact structures are implemented, then interconnection density increases, but device complexity increases

Engineering Contradiction:
Improveinterconnection densityVSAvoidconductive line structure complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The complex 3D interconnection structure is segmented into discrete, manageable components: individual conductive lines oriented in specific directions, separate staircase contact regions for different tiers, and modular repeating units. Each segment can be independently fabricated and controlled, reducing the practical complexity despite the overall 3D complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11903183B2Conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices
Publication Date: 2024.02.13 MICRON TECHNOLOGY INC
  • US11903183B2 patent drawing
  • US11903183B2 patent drawing
  • US11903183B2 patent drawing

AI summary

Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.