3D Semiconductor Staircase Contacts for Area and Power Reduction
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Solution Overview
Problem
In 3D semiconductor devices, the tight Y-pitch of multilayered connectors to word line decoders leads to increased power consumption and signal disturbance, while reducing the number of string selection lines to mitigate these issues results in high pattern density in the layer fan-out area, posing challenges for scaling down and achieving efficient data storage and operation.
Innovation Solution
The implementation of staircase contacts extending to the bottom layer with bottom contacts that connect multilayered connectors to the substrate, allowing for reduced area requirements and addressing high-density fan-out issues by enabling flexible configurations and improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the Y-pitch of multilayered connectors is reduced to connect to word line decoder, then the device area is reduced, but power consumption increases and signal disturbance occurs
Solution Approach 1:
The patent transitions from a planar connection architecture to a three-dimensional stacked architecture. Connectors extend vertically through multiple layers to reach the bottom contact layer, enabling connections in the vertical dimension rather than relying solely on horizontal routing. This dimensional change allows for reduced device area while maintaining acceptable power consumption and signal integrity characteristics.
Solution Approach 2:
The device is divided into multiple stacked layers with distinct functional regions. The connector structure is segmented into portions extending through different layers, with each layer containing specific components (active layers, insulating layers, connectors). This segmentation allows for optimized local connections while reducing overall device footprint and power consumption.
2Use of energy by stationary object
If the number of string selection lines is reduced to mitigate power consumption and signal disturbance, then power consumption decreases, but pattern density in the layer fan-out area increases
Solution Approach 1:
The patent resolves the pattern density issue by moving selection line connections to the vertical dimension. Instead of routing multiple selection lines horizontally across the device (which creates high pattern density), connectors extend vertically through layers to connect to bottom contact layers. This dimensional transition reduces the number of horizontal interconnections needed while maintaining device functionality.
Solution Approach 2:
The bottom contact layer serves as an intermediary structure that simplifies the connection architecture. By providing a common contact plane at the bottom, multiple connectors can converge to fewer selection lines, reducing the number of string selection lines needed while managing pattern density in the fan-out area.
3Area of stationary object
If staircase contacts are extended to the bottom layer, then device area is reduced and electrical performance is improved, but manufacturing complexity increases
Solution Approach 1:
The staircase contact structure is segmented into discrete portions, each extending through specific layers to designated contact regions. This segmentation allows for systematic manufacturing processes where each segment can be formed using standard semiconductor fabrication techniques, managing complexity through modular construction.
Solution Approach 2:
The patent employs preliminary patterning and layer formation steps to prepare the structure for staircase contact formation. By pre-organizing the multi-layer stack with properly positioned active layers, insulating layers, and contact regions, the subsequent formation of extended connectors becomes more straightforward, reducing overall manufacturing complexity despite the three-dimensional structure.
Data Source
AI summary
A three-dimensional (3D) semiconductor device is provided, comprising a substrate having a staircase region comprising N steps, wherein N is an integer one or greater; a stack having multi-layers on the substrate, and the multi-layers comprising active layers alternating with insulating layers on the substrate, the stack comprising a plurality of sub-stacks formed on the substrate and the sub-stacks disposed in relation to the N steps to form respective contact regions; and a plurality of connectors formed in the respective contact regions, and the connectors extending downwardly to connect a bottom layer under the multi-layers.