3D Memory Array Staircase Contacts for Over-Etch Control
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in achieving high device density, reliable word line contact connectivity, and stability due to hydrogen diffusion and over-etching issues, which affect the performance and manufacturing costs of 3D stacked memory arrays.
Innovation Solution
A 3D stacked memory array design with a staircase contact structure and conductive vias that utilize etching loading effects to prevent over-etching, combined with low-hydrogen dielectric materials to reduce defects and improve stability, and a ferroelectric memory film for efficient data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used for contact structures, then manufacturing is simpler, but over-etching occurs causing word line connectivity issues
Solution Approach 1:
The contact structure is divided into multiple segments: a base contact portion and an extended contact portion that protrudes laterally. This segmentation allows the etching process to be more precise by creating distinct zones with different etching depths, preventing over-etching while maintaining connectivity.
Solution Approach 2:
The contact structure extends in a lateral dimension beyond the vertical depth, creating an extended contact portion that protrudes sideways. This dimensional change provides an additional pathway for electrical connectivity without requiring deeper etching, thus avoiding over-etching issues.
2Reliability
If standard dielectric materials are used, then manufacturing is easier, but hydrogen diffusion causes defects and instability
Solution Approach 1:
The dielectric material is modified by changing its hydrogen content parameter, using low-hydrogen materials instead of conventional high-hydrogen materials. This parameter change prevents hydrogen diffusion into the memory cell stack, eliminating defects and improving device stability.
Solution Approach 2:
The patent employs composite material structures with specific low-hydrogen dielectric layers positioned between the contact structures and the memory cell stack. These composite materials provide both electrical isolation and hydrogen barrier functions simultaneously.
3Quantity of substance
If 3D stacked architecture is implemented, then device density increases, but word line contact connectivity becomes more difficult
Solution Approach 1:
The contact structures utilize lateral extension in addition to vertical depth, creating extended contact portions that protrude sideways. This dimensional approach provides multiple pathways for electrical connectivity through the stacked structure, ensuring reliable word line connections in 3D architectures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances device density, reduces manufacturing costs, and improves connectivity and stability of word lines by preventing over-etching and minimizing hydrogen diffusion, resulting in a reliable and efficient 3D memory array.
Implementation Method 1
An etching loading effect is used to prevent over etching of the openings and upper-layer word line shorts for the staircase vias due to a large difference in step heights between upper and lower layers
Implementation Method 2
low-hydrogen dielectric materials to reduce defects and improve stability
Implementation Method 3
a ferroelectric memory film for efficient data storage
Data Source
AI summary
A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths.