Doped Staircase Dielectric Fill for Deep Vertical Memory Arrays
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Solution Overview
Problem
The increasing depth and volume of staircase structures in vertical memory arrays pose challenges during microelectronic device fabrication, including issues with insulative material patterning, shrinkage, delamination, residual stresses, and outgassing, particularly as the number of memory cells and steps increases.
Innovation Solution
A doped dielectric material is formed using plasma enhanced chemical vapor deposition with tetraethyl orthosilicate and oxygen, doped with boron, phosphorus, fluorine, and carbon, which exhibits improved properties such as high step coverage, reduced tensile stress, and lower moisture outgassing, suitable for large gap fill applications and high aspect ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells and tiers is increased to increase memory density, then memory density is improved, but the depth of staircase structures increases causing fabrication difficulties
Solution Approach 1:
The staircase structure is divided into multiple individual steps, each providing contact regions for conductive structures. This segmentation allows the deep structure to be formed through iterative deposition and etching processes, making the fabrication of deep staircase structures manageable even as memory density increases
Solution Approach 2:
The insulative material is deposited conformally over the staircase structure before the conductive contact structures are formed. This preliminary action ensures that the insulative material is in place to provide proper isolation and electrical properties before subsequent processing steps
2Volume of stationary object
If the volume of insulative material is increased to fill deeper staircase structures, then coverage is improved, but shrinkage and delamination occur
Solution Approach 1:
The insulative material is doped with boron, phosphorus, fluorine, and carbon to modify its physical and chemical properties. This doping changes the material parameters to reduce tensile stress, minimize shrinkage, and prevent delamination, allowing large volumes of insulative material to be used without reliability issues
Solution Approach 2:
The insulative material is formed as a composite by doping silicon oxide with multiple elements (boron, phosphorus, fluorine, carbon). This composite material combines the insulating properties of silicon oxide with the stress-reducing and shrinkage-minimizing properties of the dopants
3Quantity of substance
If the depth of staircase structures is increased to accommodate more memory cells, then memory capacity is improved, but residual stresses and outgassing increase
Solution Approach 1:
Doping the insulative material with boron, phosphorus, fluorine, and carbon changes the material's physical properties to reduce residual stresses and minimize outgassing, allowing deep staircase structures to be formed without these harmful effects
Solution Approach 2:
The doping process, which could be seen as adding complexity, actually converts potential harm (stresses and outgassing) into benefit by creating a more stable insulative material that prevents these issues in deep staircase structures
4Ease of manufacture
If conventional dielectric materials are used to fill staircase structures, then material availability is improved, but chemical mechanical planarization rates decrease
Solution Approach 1:
The doped dielectric material combines silicon oxide with boron, phosphorus, fluorine, and carbon dopants to create a composite material that maintains ease of manufacture through standard deposition processes while achieving significantly improved chemical mechanical planarization rates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The doped dielectric material effectively fills insulative regions with reduced shrinkage and stress hysteresis, enhancing the fabrication process by improving chemical mechanical planarization rates and maintaining structural integrity, thus addressing the challenges associated with deep staircase structures.
Implementation Method 1
A doped dielectric material is formed using plasma enhanced chemical vapor deposition with tetraethyl orthosilicate and oxygen, doped with boron, phosphorus, fluorine, and carbon
Data Source
AI summary
A microelectronic device comprises a stack structure comprising a stack structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, staircase structures within the stack structure and having steps comprising edges of the tiers, and a doped dielectric material adjacent the steps of the staircase structures and comprising silicon dioxide doped with one or more of boron, phosphorus, carbon, and fluorine, the doped dielectric material having a greater ratio of Si—O—Si bonds to water than borophosphosilicate glass. Related methods of forming a microelectronic device and related electronic systems are also disclosed.