Staircase Edge Formation in Vertical Semiconductor Devices
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Solution Overview
Problem
The complexity and cost of photolithography processes in manufacturing vertical type semiconductor devices are increased due to the need for multiple steps in forming vertically integrated thin film layers, which complicates the manufacturing of semiconductor memory devices.
Innovation Solution
A method involving the formation of a staircase shaped edge portion in the connection region by alternately etching sacrificial layers and insulating interlayers, using a combination of etching mask patterns and photoresist patterns to reduce the number of photolithography steps and simplify the manufacturing process, with the use of materials like silicon nitride for sacrificial layers and silicon oxide for insulating interlayers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithography process steps are used to form vertically integrated thin film layers, then the manufacturing precision and structural complexity of vertical semiconductor devices are improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent divides the formation of vertically integrated layers into multiple sacrificial layer structures formed at different heights. Each sacrificial layer (first, second, third sacrificial layers) serves as a discrete segment that can be independently formed and removed, simplifying the overall photolithography process while maintaining manufacturing precision for vertical semiconductor devices
Solution Approach 2:
The patent performs preliminary actions by forming all necessary sacrificial layers and insulating layers before the final active layer formation. The sacrificial layers are pre-positioned at specific heights and configurations, allowing subsequent processes to proceed without requiring complex in-situ adjustments during photolithography steps
2Device complexity
If multiple photolithography process steps are used to form vertically integrated thin film layers, then the structural complexity of vertical semiconductor devices is improved, but the manufacturing time and productivity are reduced
Solution Approach 1:
The patent merges multiple layer formation operations into a unified process flow where sacrificial layers and insulating layers are formed together in an alternating sequence. This combining of operations reduces the total number of separate photolithography steps required, thereby improving manufacturing productivity while achieving the desired structural complexity
Solution Approach 2:
The patent employs periodic action through the alternating formation of sacrificial layers and insulating layers in a repeating sequence. This periodic pattern allows for systematic and efficient manufacturing of vertically integrated structures, reducing overall process time compared to non-periodic, step-by-step formation methods
3Reliability
If traditional photolithography methods are used to form connecting structures, then the reliability of electrical connections is maintained, but the manufacturing cost and process complexity increase
Solution Approach 1:
The patent extracts the connecting structure formation from the main active device fabrication process by using separate sacrificial layers specifically dedicated to connection region formation. This extraction allows the connecting structures to be formed independently with simplified processes while maintaining their electrical connection reliability
Solution Approach 2:
The patent uses sacrificial layers as intermediary structures that facilitate the formation of connecting structures. These intermediary sacrificial layers are formed between the active device regions and the final connecting structures, enabling easier manufacturing of connections while ensuring reliable electrical pathways are established
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces the number of photolithography steps, and achieves a uniform staircase shaped edge portion, enhancing the efficiency and cost-effectiveness of producing vertically integrated semiconductor devices with minimal process variation.
Implementation Method 1
a step of etching the exposed top sacrificial layer and an insulating interlayer below the exposed top sacrificial layer to expose a second sacrificial layer
Data Source
AI summary
A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.