Staircase Contact Structure With Etch Stop to Prevent Punch-Through
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Solution Overview
Problem
Conventional methods for forming vertical memory arrays in microelectronic devices, such as NAND Flash memory devices, face issues like conductive contact structure punch-through and material inconsistencies at staircase structures, leading to undesirable defects and reduced reliability and durability due to increased feature packing densities and decreased margins for formation errors.
Innovation Solution
The method involves forming a microelectronic device structure with a preliminary stack of insulative and sacrificial materials, applying liner materials to protect the stack during processing, and using a resist patterning and doping process to create etch stop structures that mitigate damage during contact opening formation, allowing for the formation of conductive contact structures without punch-through and material inconsistencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional methods are used to form conductive contact structures on staircase structures, then memory density can be increased, but punch-through damage occurs resulting in current leaks and short circuits
Solution Approach 1:
The patent applies preliminary action by forming protective dielectric structures (mesa nitride) and sacrificial insulative structures before forming the conductive contact structures. These protective structures are prepared in advance to prevent punch-through damage during the subsequent contact formation process, thereby maintaining both high memory density and device reliability.
Solution Approach 2:
The patent implements beforehand cushioning by creating dielectric pad structures that act as protective barriers before the conductive contact structures are formed. These cushioning structures absorb and distribute the stress during contact formation, preventing direct damage to the underlying conductive structures and eliminating current leakage paths.
2Quantity of substance
If feature packing densities are increased to improve memory density, then more memory cells fit in unit area, but margins for formation errors decrease leading to defects
Solution Approach 1:
The patent applies parameter changes by modifying the structural parameters of the staircase features, specifically increasing the width and adjusting the geometry of the steps. This provides larger process windows and greater margins for formation errors, enabling high memory density to be achieved while maintaining manufacturing precision and reducing defects.
3Ease of manufacture
If replacement gate processing is used to form stack structures, then conductive structures can be formed, but material inconsistencies and voiding occur at staircase steps
Solution Approach 1:
The patent introduces intermediary sacrificial insulative structures and dielectric pad structures that mediate between the replacement gate processing and the final stack structure formation. These intermediary structures provide a stable foundation that prevents material inconsistencies and voiding, ensuring uniform material composition throughout the stack while maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and durability of microelectronic devices by reducing the risk of contact structure punch-through and current leakage, improving the formation of conductive contacts, and maintaining device performance and memory density.
Implementation Method 1
doping at least one portion of the second liner material with a dopant
Data Source
AI summary
A microelectronic device comprises a stack structure, a staircase structure, a first liner material, an etch stop structure, and conductive contact structures. The stack structure includes conductive structures and insulative structures arranged in tiers. The stack structure includes sidewalls horizontally bounding the staircase structure. The staircase structure has steps includes edges of tiers of the stack structure. The first liner material is on the steps and the sidewalls and includes horizontally extending portions on the steps and vertically extending portions on the sidewalls. The etch stop structure is on the horizontally extending portions of the first liner material, the vertically extending portions of the first liner material being free of the etch stop structure. The conductive contact structures extend through the etch stop structure and the first liner material and to the conductive structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.