3D Staircase Lead-Out Structure for Dense Semiconductor Layer Routing
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Solution Overview
Problem
The challenge in three-dimensional semiconductor devices is to design a lead-out structure that occupies less layout space while effectively transmitting electrical signals across multiple stacked signal transmission layers, such as bit lines or word lines, due to the limitations of lithography machines in reducing critical dimensions.
Innovation Solution
A staircase structure is designed where the features of steps are integrated onto conductive pillars, allowing them to conduct electricity and make electrical contact with conductive layers at different levels, reducing the overall horizontal area occupied by the structure while ensuring each conductive layer's electrical signal is led out through one conductive pillar.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked layers of signal transmission layers is increased to achieve higher storage density, then the storage density is improved, but the layout space occupied by lead-out structures increases
Solution Approach 1:
The patent merges the step structure and conductive pillars into an integrated staircase structure. Multiple conductive layers are stacked vertically with each layer containing conductive pillars that extend through insulating layers, creating a compact three-dimensional lead-out structure that reduces horizontal layout space while maintaining signal transmission capability across multiple layers.
Solution Approach 2:
The patent transitions from a two-dimensional planar layout to a three-dimensional vertical stacking architecture. Signal transmission layers are stacked in the vertical direction (first direction) with conductive layers and insulating layers alternating, allowing higher storage density without proportionally increasing the horizontal footprint.
2Reliability
If traditional lead-out structures are used for multiple stacked layers, then signal transmission is achieved, but the horizontal area occupied by the structure increases
Solution Approach 1:
The patent implements a nested structure where conductive pillars are embedded within insulating layers, which are in turn surrounded by conductive layers. Each conductive layer contains multiple sub-conductive layers spaced apart, with conductive pillars nested within the insulating material, creating a compact nested architecture that reduces horizontal area while maintaining electrical isolation and signal transmission.
Data Source
AI summary
Disclosed are a staircase structure, a method for manufacturing the same, and a semiconductor structure. The staircase structure includes: a plurality of conductive layers spaced apart along a first direction and a plurality of step structures spaced apart along a second direction. Each conductive layer includes at least two sub-conductive layers spaced apart along a second direction, and the conductive layer extends along a third direction. One column of the sub-conductive layers being in contact connection with at least one step structure. Each step structure includes a plurality of conductive pillars electrically insulated from each other. One conductive pillar is in contact connection with one sub-conductive layer, and the conductive pillar in contact connection with the one sub-conductive layer is electrically insulated from the other sub-conductive layers. In a column of the conductive layers, the conductive layers are in contact connection with the conductive pillars in a one-to-one manner.