3D Semiconductor Memory Staircase Contacts for Dense Stacking
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Solution Overview
Problem
The integration density of two-dimensional semiconductor devices is limited due to the high cost of equipment required for pattern miniaturization, necessitating the development of three-dimensional semiconductor memory devices with memory cells arranged vertically.
Innovation Solution
The semiconductor memory device incorporates a stacked structure with a cell region and staircase portions extending in a specific direction, featuring contact plugs that penetrate both stacked structures but are electrically connected only to one structure, allowing for reduced size and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional stacked structures with multiple layers extending in the vertical direction. This dimensional change allows memory cells to be arranged in multiple stacks, significantly increasing integration density without requiring proportionally more complex manufacturing processes, as the same fabrication techniques can be applied iteratively to each layer.
2Quantity of substance
If pattern miniaturization is pursued to increase integration density, then device size is reduced, but equipment cost increases
Solution Approach 1:
Instead of continuing to miniaturize patterns in two dimensions which requires increasingly expensive equipment, the patent employs vertical stacking to achieve higher integration density. This approach maintains compatibility with existing manufacturing equipment while dramatically increasing the number of memory cells per unit area through the third dimension.
Solution Approach 2:
The patent combines multiple memory cell layers into a single integrated stacked structure, sharing common components such as bit lines and word lines across layers. This merging reduces the total number of separate components needed and allows existing manufacturing equipment to produce higher-density devices without proportional cost increases.
3Quantity of substance
If three-dimensional stacked structures are implemented, then integration density is increased, but device complexity increases
Solution Approach 1:
The patent divides the memory device into multiple discrete stacked structures, each containing a manageable number of memory cell layers. This segmentation allows complex three-dimensional integration to be achieved through repetition of standardized modular units, simplifying manufacturing and reducing overall structural complexity compared to a single monolithic stacked structure.
Data Source
AI summary
A semiconductor memory device includes; a first stacked structure including a first staircase portion, a second stacked structure on the first stacked structure and including a second staircase portion overlapping the first staircase portion, a first contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the first stacked structure and not electrically connected to the second stacked structure, and a second contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the second stacked structure and not electrically connected to the first stacked structure.