Staircase Memory Chip Stacking for Signal-Integrity Interconnects
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Solution Overview
Problem
Current semiconductor packages with stacked memory chips face challenges in high-density, high-speed operations due to limitations in interconnect efficiency and signal integrity, particularly in three-dimensional (3D) configurations.
Innovation Solution
A semiconductor package design featuring a substrate with bond fingers, master and slave memory chips stacked in a staircase shape, where pads and bonding wires are separately disposed according to functions and channels, utilizing external and internal bonding wires to connect signal and power pads independently, thereby simplifying interconnections and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chips are stacked in 3D configuration for high capacity, then storage density is improved, but interconnect efficiency and signal integrity deteriorate
Solution Approach 1:
The pad structure is segmented into three distinct types: external pads for signal transmission, internal pads for inter-chip connections, and power pads for power supply. This segmentation allows each pad type to be optimized independently, with signal pads positioned for optimal signal integrity and power pads positioned for stable power distribution, thereby maintaining signal quality in 3D stacked configurations
Solution Approach 2:
The patent transitions from planar 2D packaging to three-dimensional stacked architecture with offset positioning. Memory chips are stacked vertically with lateral displacement, creating a staircase-like 3D structure that increases storage density while managing interconnect complexity through spatial distribution across multiple dimensions
2Productivity
If pads and bonding wires are separately disposed according to functions, then interconnect efficiency is improved, but device complexity increases
Solution Approach 1:
The bonding wire structure is designed with universal functionality to serve multiple purposes: signal transmission through external bonding wires, inter-chip communication through internal bonding wires, and power distribution through power bonding wires. This multi-functional wire system reduces the need for separate dedicated structures for each function, thereby improving interconnect efficiency without proportionally increasing device complexity
Solution Approach 2:
Different regions of the semiconductor device are assigned specialized qualities: external pads and their associated bonding wires are optimized for signal transmission with appropriate impedance control, internal pads are optimized for compact inter-chip connections, and power pads are optimized for low-impedance power distribution. This local optimization allows each region to perform its function efficiently while the overall system maintains manageable complexity
Data Source
AI summary
A semiconductor package includes a substrate having bond fingers; a master memory chip mounted on the substrate; and a slave memory chip stacked over the master memory chip. The master memory chip includes master external pads and master internal pads disposed adjacent to a first side edge of the master memory chip; and master power pads disposed adjacent to a second side edge of the master memory chip. The slave memory chip includes slave external pads and slave internal pads disposed adjacent to a first side edge of the slave memory chip; and slave power pads disposed adjacent to a second side edge of the slave memory chip. A portion of the bond fingers is electrically connected to the master external pads through external bonding wires. The master internal pads are electrically connected to the slave internal pads through internal bonding wires, respectively, and the slave external pads are floated.