Staircase Memory Stack Support to Prevent Collapse and Capacitance
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Solution Overview
Problem
Vertical memory array technologies face challenges with stack collapse during processing and increased parasitic capacitance due to decreasing dimensions and spacing, which affect memory device reliability and performance.
Innovation Solution
The formation of sacrificial structures that extend entirely through the stack structure provides structural support and reduces parasitic capacitance by allowing conductive contacts to terminate at a single location, rather than varying depths, thereby preventing damage and misalignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of the stacks increases to facilitate additional memory cells, then memory density is improved, but the stacks become prone to toppling or collapse during processing
Solution Approach 1:
The stack structure is divided into multiple tiers with insulative structures and conductive structures alternating vertically. This segmentation provides internal support within the stack, preventing collapse while maintaining height for increased memory density.
Solution Approach 2:
Different regions of the stack have different structural properties. The insulative structures provide localized support at specific heights, creating a distributed support system that maintains overall stack stability without compromising memory cell capacity.
2Quantity of substance
If the dimensions and spacing of conductive features decrease, then memory density is improved, but parasitic capacitance between adjacent conductive features increases
Solution Approach 1:
Conductive structures at different tiers are connected through conductive contact structures to form equipotential regions. This reduces voltage differences between adjacent conductive features, thereby minimizing parasitic capacitance effects while maintaining compact dimensions.
Solution Approach 2:
Insulative structures serve as intermediary barriers between adjacent conductive features. These insulative tiers reduce direct electrical coupling and parasitic capacitance between conductive elements that are closely spaced to achieve high memory density.
Data Source
AI summary
A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.