Staircase Memory Device Vertical String Driver Alignment
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Solution Overview
Problem
In NAND memory devices, the arrangement of string driver transistors affects die area, die performance, and system metrics, as they need to support high voltages and occupy significant space, impacting contact area and block height dimensions, and the increasing number of word line tiers further complicates die size and peripheral device deposition.
Innovation Solution
A memory device with a staircase structure of word line tiers and a string driver structure with transistors that are vertically aligned with the staircase structure, along with a metal routing structure, allowing for efficient use of space and improved performance by individually addressing each word line tier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If string driver transistors are arranged to support high voltages and break down conditions, then reliability is improved, but die area increases
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional vertical stacking of string driver transistors. Multiple string driver transistors are stacked vertically to individually address different word line tiers, enabling high voltage support and reliability while reducing lateral die area occupation.
Solution Approach 2:
The patent implements nested vertical stacking where string driver transistors are positioned over staircase structures and memory cell strings. The string driver transistors are vertically nested above the staircase structures, with source/drain regions aligned to contact word line tiers through the stacked architecture.
2Quantity of substance
If the number of word line tiers increases, then memory capacity is improved, but total string driver area increases
Solution Approach 1:
The patent uses vertical stacking to address increased memory capacity requirements. Instead of expanding string driver area laterally with more word line tiers, the solution stacks string driver transistors vertically, with each transistor individually addressing specific word line tiers through aligned source/drain regions.
Solution Approach 2:
The patent segments the string driver function into multiple vertically stacked transistors, where each transistor individually addresses specific word line tiers. This segmentation allows parallel operation of multiple string drivers, increasing memory capacity without proportionally increasing total string driver area.
3Area of stationary object
If string driver transistors are vertically aligned with staircase structure, then die space is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of string driver transistors and staircase structures into a unified vertical alignment process. The source/drain regions of string driver transistors are formed to contact word line tiers through the staircase structures in a single aligned process, reducing die space while managing manufacturing complexity through process integration.
Solution Approach 2:
The patent performs preliminary alignment and bonding of metal routing structures to the staircase structure before final string driver transistor formation. This preliminary action establishes the vertical alignment framework, making subsequent manufacturing steps more straightforward despite the complex three-dimensional architecture.
4Productivity
If metal routing structure is vertically aligned with staircase structure, then device efficiency is improved, but deposition complexity increases
Solution Approach 1:
The patent performs preliminary alignment and bonding of the metal routing structure to the staircase structure before completing the string driver transistor formation. This preliminary action establishes the vertical alignment and electrical connections, improving device efficiency while managing deposition complexity through staged manufacturing.
Solution Approach 2:
The patent transitions metal routing from planar to vertical three-dimensional alignment with the staircase structure. The metal routing structure is deposited and bonded in vertical alignment, enabling efficient electrical connections between string driver transistors and word line tiers while reducing lateral routing complexity.
Data Source
AI summary
Memory device and formation method are provided. The memory device includes a substrate; a staircase structure on the substrate; a string driver structure over the staircase structure on a side opposite to the substrate; and a metal routing structure, between the string driver structure and the staircase structure along a vertical direction with respect to a lateral surface of the substrate. The staircase structure includes a plurality of word line tiers. The string driver structure includes a plurality of transistors to individually address the plurality of word line tiers. The string driver structure and the metal routing structure are vertically aligned with the staircase structure based on a lateral central region of the staircase structure.