Staircase Memory Array Vertical Interconnects
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Solution Overview
Problem
Current memory devices face challenges in achieving high element density and small size while maintaining manufacturing efficiency, as existing designs often require precise alignment and shared thermal cycles for the memory array chip stack and periphery wafer, which can interfere with each other's manufacturing processes.
Innovation Solution
The memory device features a periphery wafer with a memory array chip stack in a staircase configuration, utilizing a large number of conductive contacts between the wafer and chip stack to enable high-density and high-speed operation, allowing for separate optimization of manufacturing conditions for each component and reducing alignment costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the memory array chip stack and periphery wafer are disposed laterally adjacent to each other with shared thermal cycles, then manufacturing process integration is achieved, but precise alignment is required and manufacturing processes interfere with each other
Solution Approach 1:
The patent transitions from lateral adjacency (2D plane arrangement) to vertical stacking (3D arrangement) by disposing the memory array chip stack on top of the periphery wafer. This dimensional change eliminates the need for precise lateral alignment while enabling high-density interconnection through vertical conductive contacts that penetrate through the chip stack to the periphery wafer.
2Productivity
If a large number of conductive contacts are formed between periphery wafer and memory array chip stack, then high element density and high speed are achieved, but device complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension to route numerous conductive contacts through the chip stack to the periphery wafer. This vertical interconnection approach allows a large number of contacts to be implemented without increasing lateral footprint or complexity, as all contacts are organized in the vertical dimension rather than requiring complex lateral routing.
Solution Approach 2:
The patent merges the functions of multiple conductive contacts into a unified vertical interconnection structure. By combining multiple signal, power, and ground lines into vertically stacked conductive paths, the design achieves high element density while managing complexity through functional integration rather than separate lateral traces.
3Ease of manufacture
If memory array chip stack is disposed on periphery wafer, then separate optimization of manufacturing conditions is enabled, but additional vertical interconnection structures are required
Solution Approach 1:
The vertical stacking architecture enables independent manufacturing optimization by separating the periphery wafer and chip stack into distinct manufacturing stages. The conductive contacts are formed in the vertical dimension, allowing each component to be manufactured under optimized conditions separately before final assembly, without requiring complex lateral interconnection structures.
Data Source
AI summary
A memory device includes a periphery wafer, a memory array chip stack, and a plurality of first conductive contacts. The periphery wafer has a functional surface. The memory array chip stack is disposed on the periphery wafer and has a functional surface, in which the functional surface of the periphery wafer faces toward the functional surface of the memory array chip stack, and a first side of the memory array chip stack is in a staircase configuration. The first conductive contacts are on the first side of the memory array chip stack, and between and interconnecting the functional surface of the periphery wafer and the functional surface of the memory array chip stack.