Staircase Memory Structure With Via Landings for Dense Array Routing
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Solution Overview
Problem
Conventional vertical memory arrays face challenges in efficiently providing connections to each memory cell due to the increasing number of conductive connections required as the number of tiers and memory cells increases, leading to space constraints and performance issues.
Innovation Solution
The use of an elongated stair step conductive structure with contacts extending through at least a portion of the structure, allowing for direct communication with semiconductor devices and reducing the need for external connections, thereby simplifying the routing of access lines and reducing the complexity of the conductive structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of tiers and memory cells in a vertical memory array is increased to achieve higher memory density, then the memory capacity increases, but the number of conductive connections required increases, leading to space constraints and routing complexity
Solution Approach 1:
The patent implements a nested structure where conductive plates are stacked vertically with memory cells formed between them. Each conductive plate serves multiple functions: acting as a control gate for memory cells in adjacent tiers, providing electrical connections, and serving as a structural element. This nesting allows multiple memory cells to share common conductive connections, reducing the total number of connections required compared to a conventional planar architecture where each cell would require separate word lines and bit lines.
Solution Approach 2:
The patent transitions from a two-dimensional planar memory architecture to a three-dimensional vertical architecture by stacking conductive plates and memory cells in the vertical dimension. This dimensional change allows memory capacity to scale with the number of tiers without proportionally increasing the lateral footprint or the complexity of conductive routing, as connections are established vertically through the stack rather than laterally across the substrate.
2Adaptability or versatility
If the number of conductive connections is increased to support more memory cells, then more memory cells can be accessed, but the pitch of the conductive structure must be increased to accommodate the additional connections
Solution Approach 1:
Each conductive plate in the vertical stack serves multiple functions simultaneously: it acts as a control gate for memory cells in adjacent tiers, provides electrical connection pathways, and serves as a structural element separating tiers. This multi-functionality allows a single conductive plate to replace what would traditionally require multiple separate conductive elements (word lines, bit lines, select gates), thereby maintaining high memory cell accessibility without increasing the lateral pitch of the conductive structure.
3Quantity of substance
If conventional vertical memory arrays are used with multiple conductive connections per memory cell, then memory density can be increased, but it becomes difficult to provide connections to each memory cell in an effective and efficient manner
Solution Approach 1:
The patent segments the memory array into multiple tiers, with each tier containing memory cells formed between adjacent conductive plates. This segmentation allows the memory array to be divided into manageable units that can be independently addressed and controlled. Each conductive plate controls memory cells in specific tiers, creating a segmented addressing scheme that simplifies the routing and control logic compared to a monolithic structure where all cells would require direct access to all conductive lines.
Data Source
AI summary
Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.