Staircase Memory Structures Mitigating Feature Damage
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Solution Overview
Problem
Conventional methods for forming vertical memory arrays in non-volatile memory devices, such as NAND Flash memory, often result in undesirable damage like walk-off, lift-off, and corrosion-based damage during the formation of features, which affects the integrity and reliability of the memory devices.
Innovation Solution
A microelectronic device structure with a stack structure comprising alternating conductive and insulative materials in tiers, divided by dielectric-filled slots, and a source tier with distinct conductive structures and contact structures that mitigate damage by providing stable electrical connections and preventing feature fall-off during formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional methods are used to form vertical memory arrays, then memory density can be increased, but undesirable damage such as walk-off, lift-off, and corrosion-based damage occurs during feature formation
Solution Approach 1:
The patent applies preliminary action by forming a protective coating on the memory device structure before subsequent processing steps. This coating is deposited in advance to prevent damage during later fabrication processes, specifically addressing walk-off and lift-off issues by creating a protective barrier that maintains feature integrity throughout the manufacturing sequence.
Solution Approach 2:
The patent introduces an intermediary protective coating layer that acts as a mediator between the memory device features and the processing environment. This coating layer prevents direct interaction between corrosive materials and the underlying conductive and insulative structures, thereby eliminating corrosion-based damage while allowing the memory density to be increased through vertical stacking.
2Ease of operation
If staircase structures are formed to provide electrical connections, then access to conductive structures is enabled, but damage occurs during the formation of additional features
Solution Approach 1:
The protective coating is formed before the staircase structures and subsequent contact structures are created. This preliminary protective layer remains in place during the formation of electrical connections, preventing damage to the staircase features and underlying conductive structures while maintaining ease of electrical access to the memory cells.
Solution Approach 2:
The protective coating serves as an intermediary that allows electrical connections to be formed through the staircase structures without exposing the underlying features to damaging conditions. The coating can be selectively removed or is designed to be transparent to the connection formation process while protecting against corrosion and mechanical damage during subsequent processing.
Data Source
AI summary
A microelectronic device is disclosed, comprising: a stack structure comprising vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, the stack structure having blocks separated from one another by filled slot structures; a source tier structure underlying the stack structure and comprising: a merged conductive structure adjacent a first discrete conductive structure in a first direction; and a second discrete conductive structure in the first direction that is spaced apart from the merged conductive by the first discrete conductive structure; a first support contact structure on the first discrete conductive structure; and a subsequent support contact structure on the merged conductive structure and adjacent the first support contact in the first direction, wherein one of the filled slot structures is vertically directly above at least a portion of the merged conductive structure.