Staircase MIM Capacitor Layout for Higher Capacitance Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional Metal-Insulator-Metal (MIM) capacitive elements in integrated circuits occupy a large surface area due to low capacitive value per unit area, and reducing the dielectric layer thickness leads to electrical and chemical degradation, as well as topological constraints.
Innovation Solution
A capacitive element design with a low voltage dielectric layer covered by a second conductive layer, forming a staircase structure to increase capacitive value per unit area, while avoiding breakdown and etching issues, and allowing cointegration with other circuit elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of the dielectric layer is reduced to increase capacitive value per unit area, then the capacitive value per unit area increases (double to quadruple), but the breakdown voltage is reduced and tip effects generate electric fields that break down the dielectric layer
Solution Approach 1:
The patent transitions from a planar dielectric layer to a three-dimensional folded dielectric structure. The dielectric layer is folded back on itself multiple times, creating a staircase-like configuration with vertical and horizontal segments. This dimensional transformation increases the effective capacitive area without proportionally increasing the footprint area, thereby improving capacitive value per unit area while maintaining adequate dielectric thickness for breakdown resistance.
Solution Approach 2:
The folded dielectric structure implements a nesting principle where the dielectric layer is folded back onto itself, creating nested segments. Each fold creates additional capacitive plates in a compact configuration, allowing multiple capacitive elements to be nested within a small footprint while maintaining sufficient dielectric thickness in each segment.
2Quantity of substance
If the thickness of the dielectric layer is reduced to increase capacitive value per unit area, then the capacitive value per unit area increases, but chemical degradation occurs during wet etching steps due to undercut dissolution
Solution Approach 1:
The folded dielectric structure creates vertical walls and horizontal ledges that provide mechanical protection against wet etching. The etchant must navigate complex three-dimensional geometry with overhangs and protected surfaces, significantly reducing undercut dissolution compared to simple planar structures.
Solution Approach 2:
The folded dielectric structure inherently provides protective ledges and overhangs before etching occurs. These geometric features act as pre-positioned protection that shields vulnerable dielectric surfaces from direct etchant exposure, cushioning against chemical degradation during manufacturing steps.
3Quantity of substance
If the thickness of the dielectric layer is reduced to increase capacitive value per unit area, then the capacitive value per unit area increases, but bulky topological constraints are introduced
Solution Approach 1:
The folded dielectric structure divides the capacitive element into multiple discrete segments or steps. Each fold creates distinct capacitive plates separated by dielectric material, allowing the structure to be manufactured using standard segmented fabrication processes while achieving high capacitive density.
Solution Approach 2:
By folding the dielectric layer in the vertical dimension rather than simply reducing thickness, the patent achieves high capacitive value without introducing excessive lateral complexity. The vertical folding creates a compact three-dimensional structure that fits within standard device geometries.
4Adaptability or versatility
If conventional MIM capacitive elements are manufactured with joint manufacturing steps, then integration with other circuit elements is achieved, but the capacitive value per unit area is relatively low
Solution Approach 1:
The folded dielectric structure serves multiple functions: it provides high capacitive value, maintains compatibility with standard fabrication processes, and integrates with other circuit elements. The structure can be manufactured using conventional deposition and etching techniques while achieving superior capacitive density compared to planar structures.
Solution Approach 2:
The three-dimensional folded configuration allows the capacitive element to achieve high capacitive value within the constraints of standard fabrication capabilities, making it universally applicable to conventional integrated circuit manufacturing processes while outperforming two-dimensional planar structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The capacitive element achieves double to quadruple capacitive value per unit area with improved linearity and reliability, without topological constraints, and can be manufactured concurrently with other circuit components.
Implementation Method 1
capacitive element comprising: a first conductive layer disposed on a front face of a semiconductor substrate, delimited by an outline, and forming a first electrode of the capacitive element; a low voltage dielectric layer covering the first conductive layer; and a second conductive layer
Implementation Method 2
breakdown voltage of the dielectric layer is also reduced. Consequently, for operating voltages lower than the breakdown voltage, tip effects TPEF along the ridges and at the vertices of the first conductive layer 10 can generate electric fields which can break down the dielectric layer 30
Data Source
AI summary
A capacitive element includes a first conductive layer delimited by an outline and a low voltage dielectric layer covering the first conductive layer. A second conductive layer covers the low voltage dielectric layer and includes: a first portion located over a central zone of the first conductive layer which forms a first capacitor electrode; and a second portion located over the first conductive layer at the inner border of the entire outline of the first conductive layer, and over the front face at the outer border of the entire outline of the first conductive layer. The first portion and the second portion of the second conductive layer are electrically separated by an annular opening extending through the second conductive layer. The first conductive layer is electrically connected to the second portion of the second conductive layer to form a second capacitor electrode.