Staircase Semiconductor Package Encapsulation to Prevent Chip Cracking
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Solution Overview
Problem
The increasing warpage in slimmed semiconductor chips reduces the reliability of semiconductor packages due to void formation and cracking during the molding process, which is exacerbated by thermal expansion and pressure from resin solutions.
Innovation Solution
A semiconductor package design featuring a base substrate with an insulating layer having specific openings that allow resin to fill voids and prevent cracking, with semiconductor chips stacked in a staircase configuration and a molding portion that encapsulates the chips, ensuring even pressure distribution and filling of gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips are slimmed to achieve compact electronic components, then the size and weight of the package are reduced, but warpage increases leading to void formation and cracking
Solution Approach 1:
The insulating layer is segmented into multiple regions with different properties: a first region with openings for resin filling and a second region without openings for chip support. This segmentation allows the package to simultaneously accommodate slim chips while preventing warpage-induced defects through localized structural differences.
Solution Approach 2:
Different regions of the insulating layer are assigned different qualities: the first region has openings to allow resin penetration and prevent void formation, while the second region remains intact to provide mechanical support. This local differentiation addresses warpage and reliability issues without compromising the overall chip slimming objective.
2Reliability
If resin solution is applied during molding to encapsulate chips, then complete encapsulation is achieved, but pressure from the resin causes void formation and cracking in slimmed chips
Solution Approach 1:
Openings are created in the insulating layer to extract or remove the harmful effect of resin pressure. These openings allow the resin solution to pass through and fill potential void spaces without building up excessive pressure that would cause cracking in the slimmed semiconductor chips.
Solution Approach 2:
The openings in the insulating layer act as intermediaries that mediate between the resin solution and the semiconductor chips. They allow controlled resin flow and pressure distribution, preventing direct high-pressure contact between the resin and the vulnerable chip structures.
3Reliability
If openings are added to the insulating layer to prevent void formation, then reliability is improved, but the structural complexity of the package increases
Solution Approach 1:
The insulating layer is divided into functional segments (first region with openings, second region without openings) rather than uniformly modifying the entire layer. This segmentation achieves defect prevention where needed while maintaining structural simplicity in other areas, thus limiting the increase in overall device complexity.
Data Source
AI summary
A semiconductor package includes a base substrate, an insulating layer including a first region disposed on the base substrate and in which first and second openings are disposed and a second region, a remaining region of the base substrate other than the first region, a first semiconductor chip disposed on the base substrate and including bonding pads disposed closely to a first edge, at least one second semiconductor chip stacked on the first semiconductor chip in the form of a staircase toward a second edge, parallel to the first edge, and a molding portion covering the base substrate to encapsulate the first and second semiconductor chips, wherein the length of the first edge is disposed to overlap the second region, both ends of the second edge are disposed to overlap the first and second openings, and the molding portion fills the first and second openings.