Staircase Pad Structure for 3D Memory Electrical Connections
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Solution Overview
Problem
Conventional three-dimensional semiconductor devices face challenges in electrically connecting memory cells across different layers with external parts while maintaining a minimized unit area, due to the complexity of the vertical memory array structure.
Innovation Solution
A pad structure featuring staircase structures with alternately stacked conductor and dielectric layers, where adjacent staircase structures are connected by sharing these layers and have staircase portions that gradually decrease in height in opposite directions, allowing for efficient electrical connection and reduced area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical memory array structure is used to increase memory capacity within unit area, then the memory density is improved, but the electrical connection between memory cells at different layers and external parts becomes more difficult
Solution Approach 1:
The pad structure transitions from a conventional planar configuration to a three-dimensional staircase structure with multiple tiers. This dimensional change allows electrical connections to be established through vertical and diagonal pathways, enabling memory cells at different layers to connect to external parts while maintaining high density. The staircase configuration creates multiple connection points at varying heights, solving the electrical connection difficulty in vertical arrays.
Solution Approach 2:
The pad structure employs nested conductor layers within the staircase configuration, where conductor layers are embedded within dielectric layers at different levels. This nesting approach allows multiple conductive pathways to be integrated within a compact vertical space, enabling complex electrical connections between different memory cell layers and external contacts without increasing the footprint area.
2Quantity of substance
If more memory cells are arranged in vertical array to increase density, then the memory capacity per unit area is improved, but the area required for pad structure increases
Solution Approach 1:
The pad structure utilizes vertical stacking with multiple tiers arranged in a staircase pattern, transitioning from a two-dimensional planar layout to a three-dimensional configuration. This allows the pad structure to accommodate more connection points for memory cells without proportionally increasing the horizontal footprint area, thereby reducing the area required while maintaining high memory capacity.
Solution Approach 2:
Adjacent staircase structures share common conductor layers and dielectric layers, merging redundant materials and reducing overall pad structure area. This sharing approach allows multiple memory cell connections to be achieved with fewer unique material layers, compacting the pad structure and reducing the area required while supporting high memory capacity.
3Ease of manufacture
If conventional pad structure is used in three-dimensional semiconductor devices, then the manufacturing process is simple, but the device density and performance are limited
Solution Approach 1:
The pad structure is divided into multiple discrete tiers or steps, with each tier containing conductor layers, dielectric layers, and contact holes. This segmentation into manageable stages allows the complex three-dimensional structure to be manufactured using sequential deposition and etching processes, maintaining manufacturing simplicity while achieving high device density through the vertical staircase configuration.
Solution Approach 2:
The invention introduces a three-dimensional staircase configuration with multiple vertical tiers, transforming the conventional two-dimensional pad structure. This dimensional enhancement enables greater device density by utilizing vertical space more efficiently, while the modular tiered design maintains compatibility with standard semiconductor manufacturing processes through sequential layer deposition and patterning.
Data Source
AI summary
A pad structure including a plurality of staircase structures is provided. The staircase structures are disposed on the substrate. Each of the staircase structures includes a plurality of conductor layers and a plurality of dielectric layers that are alternately stacked. Two adjacent staircase structures are connected with each other by sharing the conductor layers and the dielectric layers and are arranged in parallel along a first direction. One of the two adjacent staircase structures includes at least one staircase portion that gradually decreases in height along a second direction, and the other of the two adjacent staircase structures includes at least one staircase portion that gradually decreases in height along a direction opposite to the second direction.