Staircase Region Segmentation in Nonvolatile Memory Block Width Control
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Solution Overview
Problem
In nonvolatile semiconductor memory devices, the increase in the number of control electrode layers leads to a widening of the block width, which is not effectively suppressed by existing staircase or checkerboard configurations, resulting in inefficiencies in data erasure and processing accuracy.
Innovation Solution
The implementation of a stacked body structure with alternating electrode and insulating layers, featuring staircase regions where each electrode layer has an exposed portion in a specific staircase region, reducing the number of exposed portions in the Y direction and maintaining a smaller block width even with an increase in the number of layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of control electrode layers is increased to increase memory capacity, then the memory capacity is improved, but the block width is widened
Solution Approach 1:
The stacked body is divided into multiple staircase regions, with each region containing exposed portions of electrode layers. By segmenting the exposure locations across different staircase regions, the patent reduces the number of exposed portions that need to be spaced apart in the same block, thereby suppressing block width expansion while maintaining high memory capacity through increased electrode layer count
Solution Approach 2:
The patent introduces a staircase structure that creates vertical and diagonal arrangements of exposed portions across multiple levels and regions. This dimensional arrangement allows exposed portions to be distributed in three-dimensional space rather than being confined to a single horizontal plane, enabling closer spacing while maintaining electrical isolation and reducing overall block width
2Reliability
If extraction lines are spaced from each other to prevent interference, then electrical isolation is improved, but the block width is widened
Solution Approach 1:
The patent segments the block into multiple staircase regions, with each region containing a limited number of exposed portions. This segmentation allows extraction lines to be closely spaced within each region while maintaining electrical isolation through the insulating layer structure and the spatial separation provided by the staircase configuration across regions
Solution Approach 2:
The patent introduces insulating layers as intermediary structures between adjacent extraction lines and between the channel body layer and control electrode layers. These insulating layers provide electrical isolation without requiring large spacing, enabling compact block width while maintaining reliability through controlled dielectric separation
3Quantity of substance
If the number of stairs in the staircase region is increased to accommodate more layers, then the number of exposed portions is increased, but the processing accuracy is reduced
Solution Approach 1:
By dividing the stacked body into multiple staircase regions, the patent segments the formation process into discrete, manageable units. Each staircase region can be processed independently with standardized procedures, improving manufacturing precision while collectively accommodating a large number of exposed portions across all regions through systematic segmentation
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a foundation layer; and a stacked body provided on the foundation layer, each of a plurality of electrode layers and each of a plurality of insulating layers being stacked alternately in the stacked body; a select gate electrode provided on the stacked body; and a semiconductor layer extending from an upper end of the select gate electrode to a lower end of the stacked body. The stacked body includes a plurality of staircase regions. The each of the plurality of electrode layers includes an exposed portion. The exposed portion is not covered with the plurality of electrode layers other than the each of the plurality of electrode layers and the plurality of insulating layers. And the exposed portion of each of the plurality of electrode layers is disposed in one of the plurality of staircase regions.