Staircase Semiconductor Chip Stack with Support for Deflection Control
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Solution Overview
Problem
High-integration semiconductor packages face challenges in reducing size while minimizing chip stack deflection and enabling simultaneous wire bonding on both upper and lower stacks.
Innovation Solution
A semiconductor package design featuring a substrate with a first semiconductor chip stack in a staircase configuration, a support spaced apart from the stack, and a second chip stack with pads exposed for simultaneous wire bonding, allowing for size reduction and deflection prevention by using a controller chip as a support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a plurality of semiconductor chips are stacked vertically to achieve high integration, then the integration density is improved, but the chip stack deflection increases
Solution Approach 1:
The patent implements a stacked semiconductor package structure where multiple semiconductor chips are vertically nested one on top of another. Each chip is positioned on the previous chip in the stack, creating a compact three-dimensional arrangement that achieves high integration density while maintaining structural stability through the nested configuration.
Solution Approach 2:
The patent transitions from planar two-dimensional chip arrangement to three-dimensional vertical stacking. By utilizing the vertical dimension (Z-axis) in addition to the horizontal plane, the package achieves higher integration density without increasing the footprint area, effectively resolving the contradiction between integration density and structural stability.
2Volume of moving object
If the semiconductor package size is reduced, then the miniaturization is improved, but the chip stack deflection control becomes more difficult
Solution Approach 1:
The nested stacking arrangement allows multiple chips to be positioned within a compact volume, reducing the overall package size. The vertical nesting configuration minimizes the horizontal footprint while maintaining the structural integrity of each chip in the stack, thereby controlling deflection despite miniaturization.
Solution Approach 2:
By arranging chips in the vertical dimension rather than spreading them horizontally, the patent reduces the package footprint area and volume. This three-dimensional arrangement achieves miniaturization while the vertical stacking geometry inherently provides deflection control through the layered support structure.
3Adaptability or versatility
If wire bonding is performed on upper and lower semiconductor chip stacks, then the connectivity is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the wire bonding process into separate operations for the upper chip stack and lower chip stack. By segmenting the manufacturing process into distinct stages for different chip groups, the patent achieves comprehensive connectivity while managing manufacturing complexity through systematic process division and modular fabrication approaches.
Data Source
AI summary
A semiconductor package includes a substrate, and a first semiconductor chip stack disposed on the substrate. The first semiconductor chip stack includes a plurality of first semiconductor chips. The first semiconductor chips are stacked in a staircase configuration along a first direction. A first support is disposed on the substrate. The first support is spaced apart from the first semiconductor chip stack. A second semiconductor chip stack is disposed on the first semiconductor chip stack and the first support. The second semiconductor chip stack includes a plurality of second semiconductor chips. The second semiconductor chips are stacked in a second staircase configuration along a second direction opposite the first direction. A height of the first semiconductor chip stack is substantially equal to a height of the first support.