Staircase Structures for 3D Memory Double-Sided Routing
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Solution Overview
Problem
Conventional 3D memory devices face limitations in interconnect routing due to the constraint of word line contacts landing on conventional staircase structures along a single vertical direction, leading to higher interconnect density and smaller process windows, which hampers the increase in storage capacity.
Innovation Solution
The development of staircase structures for 3D memory devices that enable double-sided routing, allowing interconnects to fan out towards both sides of the substrate, thereby reducing interconnect density and enlarging the process window, and potentially eliminating the need for high-aspect-ratio interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional staircase structures are used with single-direction routing, then the fabrication process is simpler, but interconnect density increases and process window decreases
Solution Approach 1:
The patent transitions from single-direction routing to double-sided routing by extending interconnect pathways to both sides of the substrate. This dimensional change in routing architecture allows interconnects to fan out bidirectionally, effectively halving the interconnect density on each side while maintaining overall connectivity requirements.
2Device complexity
If conventional staircase structures are used with single-direction routing, then the structure is less complex, but process window becomes smaller
Solution Approach 1:
The patent segments the routing function into two independent directions by forming staircase structures on both sides of the substrate. This segmentation allows each side to handle half the routing load independently, reducing the complexity of individual routing paths and enlarging the process window for each segmented routing operation.
3Manufacturing precision
If single-direction routing is used, then alignment is easier, but routing flexibility is reduced
Solution Approach 1:
The patent employs asymmetric staircase structures where the number of steps and their dimensions can differ between the two sides of the substrate. This asymmetric design provides tailored routing flexibility for each side based on specific interconnect requirements, while maintaining alignment feasibility through controlled step geometries and standardized fabrication processes.
Data Source
AI summary
Embodiments of methods for forming staircase structures for three-dimensional (3D) memory devices double-sided routing are disclosed. In an example, a first dielectric layer is formed on a substrate, and a first photoresist layer is formed on the first dielectric layer. A recess is patterned through the first dielectric layer to the substrate by cycles of trim-etch the first dielectric layer. A plurality of dielectric/sacrificial layer pairs filling in the recess are formed. A second photoresist layer is formed on a top surface of the dielectric/sacrificial layer pairs. The dielectric/sacrificial layer pairs are patterned by cycles of trim-etch the dielectric/sacrificial layer pairs. A second dielectric layer covering the patterned dielectric/sacrificial layer pairs is formed. A memory stack on the substrate including a plurality of conductor/dielectric layer pairs is formed by replacing, with a plurality of conductor layers, the sacrificial layers in the patterned dielectric/sacrificial layer pairs.