Staircase Structures in 3D NAND Memory Devices
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Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, traditional fabrication techniques become challenging and costly, necessitating a more efficient method for increasing memory density, which 3D memory architecture aims to address by forming staircase structures in three-dimensional memory devices.
Innovation Solution
A method for forming staircase structures in 3D memory devices involves creating alternating layer stacks over a substrate, using repetitive etch-trim processes to form and trim staircase structures, allowing for the exposure of layer stacks and the formation of vertical memory strings with conductive and insulating layers, thereby reducing fabrication complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cell feature sizes are reduced to increase memory density, then memory density improves, but fabrication complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture by stacking multiple layers of memory cells vertically. This dimensional change allows memory density to increase without requiring further reduction of feature sizes, thereby avoiding the associated fabrication complexity and cost increases.
Solution Approach 2:
The 3D memory device is divided into multiple stacked layers, each containing memory cells, word lines, and bit lines. This segmentation into discrete layers simplifies the fabrication process for each individual layer while achieving high overall memory density through vertical stacking.
2Quantity of substance
If traditional planar fabrication techniques are used to increase memory density, then memory density improves, but manufacturing cost increases
Solution Approach 1:
By moving to 3D stacking architecture, the patent achieves higher memory density without requiring increasingly complex and expensive planar fabrication techniques. The vertical stacking approach uses more manageable fabrication processes applied repeatedly across multiple layers.
Solution Approach 2:
The patent forms complete alternating layer stacks (including memory cells, word lines, and bit lines) as preliminary structures before final processing. This preliminary formation of fully functional layers simplifies subsequent fabrication steps and reduces overall manufacturing complexity and cost.
3Device complexity
If 3D memory architecture with staircase structures is implemented, then fabrication complexity reduces, but structural complexity increases
Solution Approach 1:
The staircase structure is segmented into multiple discrete steps, each corresponding to a specific layer or set of layers in the 3D memory device. This segmentation allows the complex 3D structure to be fabricated through repeated application of simpler patterning and etching processes, reducing overall fabrication complexity.
Solution Approach 2:
The staircase structure introduces controlled complexity in the vertical dimension to enable simplified fabrication. By creating stepped terraces at different heights, the patent allows for selective processing of different layers while maintaining manageable fabrication processes.
Data Source
AI summary
Disclosed is a method for forming a staircase structure of 3D memory. The method includes providing a substrate, forming an alternating layer stack over the substrate, forming a plurality of block regions over a surface of the alternating layer stack, forming a first plurality of staircase structures to expose a portion of a first number of top-most layer stacks at each of the block regions and removing the first number of the layer stacks at a second plurality of staircase structures at each of the block regions.