3D NAND Staircase Structures for Electrical Isolation
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Solution Overview
Problem
Conventional vertical memory array configurations in microelectronic devices, such as 3D NAND Flash memory devices, face issues with increased feature packing densities leading to undesirable current leaks, which diminish performance, reliability, and durability due to insufficient electrical isolation between conductive structures.
Innovation Solution
The implementation of a microelectronic device structure with a staircase structure and discrete conductive structures electrically isolated from the source tier, utilizing conductive pillar structures that extend through the stack to provide enhanced electrical isolation and prevent current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature packing density is increased to enhance memory density, then memory capacity per unit area is improved, but electrical isolation between conductive structures becomes insufficient leading to current leaks
Solution Approach 1:
The patent introduces an intermediate dielectric material positioned between adjacent conductive structures and memory strings. This dielectric intermediary prevents direct electrical contact and current leakage while allowing the conductive structures to remain in close proximity for high density. The dielectric material acts as a mediator that maintains electrical isolation without requiring increased spacing between features.
2Quantity of substance
If conventional upper deck configurations are used to increase memory density, then more memory strings can be packed vertically, but current leaks between access lines and sources occur
Solution Approach 1:
The patent extracts the electrical isolation function from the conventional deck structure and implements it through separate dielectric regions positioned between the access lines and memory strings. By taking out the isolation requirement and addressing it independently through dedicated dielectric materials, the design prevents current leaks while maintaining the high-density vertical stacking configuration.
3Manufacturing precision
If margins for formation errors are decreased to increase precision, then manufacturing accuracy is improved, but current leaks become more prevalent due to tighter tolerances
Solution Approach 1:
The patent changes the material parameter by introducing dielectric materials with appropriate electrical properties between conductive structures. This parameter change allows the system to maintain electrical isolation even when dimensional tolerances are tight, as the dielectric property provides isolation that is not solely dependent on precise geometric spacing.
Data Source
AI summary
A microelectronic device comprises vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures; a staircase structure within the stack structure and having steps comprising edges of at least some of the tiers; a source tier underlying the stack structure and comprising: a source structure, and first discrete conductive structures horizontally separated from one another and the source structure by at least one dielectric material; conductive contact structures on the steps of the staircase structure; and first conductive pillar structures horizontally alternating with the conductive contact structures and vertically extending through the stack structure to the first discrete conductive structures of the source tier. A memory device, a 3D NAND Flash memory device, and an electronic system are also described.