3D Nonvolatile Memory Staircase Word Lines for Leakage Reduction
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Solution Overview
Problem
Current flash memory systems face challenges in reducing the size and cost of memory cell arrays while managing leakage currents and parasitic currents, which affect the efficiency of data reading and programming operations in three-dimensional memory arrays.
Innovation Solution
The implementation of a 3D nonvolatile memory architecture with staircase word lines, where local bit lines are elongated in the z-direction and word lines are spaced apart with alternating steps and risers, allowing for easy access and selection of word lines from either the top or bottom, reducing the need for multiple parallel word lines and minimizing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple parallel word lines are used to access memory cells, then memory capacity and access capability are improved, but driver load and parasitic currents increase
Solution Approach 1:
The patent transitions from a planar 2D memory architecture to a 3D vertical architecture where bit lines extend through multiple stacked memory layers. This dimensional change allows memory cells to be accessed through vertical bit lines rather than requiring multiple parallel word lines, thereby reducing the number of active conductors and associated parasitic currents while maintaining memory capacity.
Solution Approach 2:
The memory array is divided into multiple stacked layers with local bit lines serving each layer. This segmentation allows independent addressing of memory cells in different layers through the same vertical bit line structure, reducing the need for multiple parallel word lines and decreasing overall driver load and parasitic current consumption.
2Adaptability or versatility
If complex interconnect structures are implemented to access multiple word lines, then memory functionality is improved, but device complexity increases
Solution Approach 1:
The patent employs a 3D vertical stacking architecture where bit lines extend perpendicular to the substrate through multiple memory layers. This eliminates the need for complex planar interconnect routing and multiple parallel word lines, simplifying the overall interconnect structure while enabling access to memory cells across multiple layers through the vertical bit line pathways.
Solution Approach 2:
The vertical bit lines serve multiple functions: they act as select lines for memory cell access, provide current pathways for read/write operations, and enable addressing of memory cells across multiple stacked layers. This multi-functionality reduces the need for separate dedicated interconnect structures for each word line, thereby simplifying the overall device complexity.
3Reliability
If diodes are added in series with memory elements to reduce leakage, then reliability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent utilizes the inherent vertical structure and material properties of the memory stack to naturally suppress leakage currents. By designing the memory elements and their surrounding dielectric structures with appropriate geometry and material selection, the architecture achieves leakage reduction without requiring additional diode components, thereby maintaining manufacturing simplicity.
Solution Approach 2:
The patent removes the need for series diodes by extracting the leakage control function into the architectural design of the vertical bit line and memory element structure. The selective activation of memory cells through vertical bit lines and the inherent isolation provided by the stacked layer structure naturally prevent leakage paths, eliminating the requirement for additional diode components and simplifying the manufacturing process.
Data Source
AI summary
In a 3D nonvolatile memory with memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate; a plurality of local bit lines elongated in the z-direction through the plurality of layers and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; the 3D nonvolatile memory further having a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, individual staircase word lines each having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane.