Stairless 3D Memory Word Lines With Integrated Layer-Via Contacts
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently forming stairless structures for vertical NAND strings, particularly in creating integrated layer-and-via structures that effectively support memory operations while maintaining device reliability and performance.
Innovation Solution
The formation of an alternating stack of insulating and sacrificial material layers, followed by the creation of memory openings, dielectric barrier structures, and integrated line-and-via structures through isotropic recessing and conductive material deposition, enables the construction of stairless three-dimensional memory devices with vertically extending interfaces and lateral offsets, facilitating efficient memory element placement and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional stairless structures are formed for vertical NAND strings, then device reliability is improved, but manufacturing complexity increases due to difficulty in forming integrated layer-and-via structures
Solution Approach 1:
The patent divides the formation process into distinct segments: first forming the alternating stack of insulating and sacrificial material layers, then creating memory openings, followed by forming dielectric barrier structures, and finally creating integrated layer-and-via structures through controlled isotropic recessing. This segmentation transforms a complex monolithic process into manageable discrete steps, reducing manufacturing complexity while maintaining reliability.
Solution Approach 2:
The patent performs preliminary actions by first forming the alternating stack structure with sacrificial material layers before creating the final conductive structures. The sacrificial layers are pre-positioned to define future via locations, and dielectric barrier structures are formed in advance to control subsequent isotropic recessing. This preliminary structuring simplifies the overall manufacturing process.
2Reliability
If integrated layer-and-via structures are formed to support memory operations, then electrical connectivity is improved, but device structure complexity increases
Solution Approach 1:
The patent merges the layer and via structures into integrated layer-and-via structures where conductive materials simultaneously form horizontal conducting layers and vertical via portions. This merging eliminates the need for separate layer formation and via formation processes, simplifying the overall structure while maintaining excellent electrical connectivity for memory operations.
Solution Approach 2:
The patent uses sacrificial material layers as intermediary structures that temporarily occupy space during manufacturing. These sacrificial layers are isotropically recessed away to create voids that are then filled with conductive material. The intermediary sacrificial layers enable precise control of via dimensions and positions without requiring complex direct patterning processes.
3Ease of manufacture
If isotropic recessing is used to form continuous voids, then manufacturing ease is improved, but precision control of via dimensions becomes more difficult
Solution Approach 1:
The patent replaces direct mechanical patterning of via structures with a chemistry-based approach using isotropic recessing of sacrificial material layers. Instead of using complex lithography and etching to directly define via dimensions, the process uses chemical isotropic recession followed by conformal deposition, substituting mechanical precision requirements with chemical process control for better manufacturability.
Solution Approach 2:
The patent controls via dimensions by changing the parameters of the isotropic recessing process, such as recessing time, temperature, and chemistry. By adjusting these parameters, precise control of void dimensions is achieved while maintaining the simplicity of the isotropic recessing approach. The conformal deposition thickness also serves as a controllable parameter for final via dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the development of reliable and efficient three-dimensional memory devices with improved memory element placement and electrical connectivity, enhancing the performance and stability of vertical NAND strings within the memory array.
Implementation Method 1
isotropically recessing the sacrificial material layers from around the pair of backside trenches and from underneath each of the plurality of via openings
Implementation Method 2
depositing at least one electrically conductive material in the continuous voids to form respective integrated layer-and-via structures in the continuous voids
Data Source
AI summary
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, memory openings are formed through the alternating stack, and memory opening fill structures including a respective vertical stack of memory elements are formed in the memory openings. The sacrificial material layers are replaced with electrically conductive layers. Electrical contacts to the electrically conductive layers may be provided by forming integrated layer-and-via structures that simultaneously forms metallic via portions as an integral portion of a continuous electrically conductive structure that includes a respective electrically conductive layer. Alternatively, electrical contacts to the electrically conductive layers may be provided by forming integrated line-and-via structures that includes a metallic plate portion contacting a respective electrically conductive layer and a metallic via portion.