Stairstep Contact Structure Formation in 3D Memory
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Solution Overview
Problem
In three-dimensional high density semiconductor devices, existing methods for connecting interlayer conductors to active layers face challenges due to variations in etching times of active and insulating layers, leading to etching depth issues and potential damage during the process.
Innovation Solution
A method is developed to form stairstep contact structures by creating sub stacks with varying etch times for insulating and active layers, allowing interlayer conductors to extend to landing areas on the active layers while being separated by insulating material, using a combination of lithographic and trim-etch processes to manage etching depths and prevent damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multiple lithographic-etch process or trim-etch process is used to connect interlayer conductors to active layers, then connections can be established in 3D stacked memory devices, but etching depth variations and potential damage occur due to different etching times of active and insulating layers
Solution Approach 1:
The patent divides the etching process into multiple selective etching steps, where different etch masks are used to target specific insulating layers between active layers. This segmentation allows precise control over which insulating layers are removed and which are retained, solving the etching depth control problem by treating each layer pair independently rather than etching through the entire stack uniformly.
Solution Approach 2:
The patent applies different etching characteristics to different regions of the structure by using etch masks that selectively expose only certain insulating layers. This local quality approach ensures that each insulating layer is treated according to its specific requirements - some are removed to create vias, while others are retained to provide electrical isolation, thereby preventing both etching depth issues and structural damage.
2Manufacturing precision
If insulating layers with different etching times are used between sub stacks, then selective etching to form vias and landing areas is enabled, but process complexity increases
Solution Approach 1:
The patent incorporates etch masks as preliminary structures that are formed before the selective etching process. These masks are strategically placed on specific insulating layers to protect them during etching, and are removed afterward. This preliminary action simplifies the overall process by providing a clear, step-by-step procedure that achieves precise via formation without requiring complex real-time control mechanisms.
Solution Approach 2:
The patent utilizes changes in etching parameters (etch time, etch selectivity) combined with etch masks to achieve different etching depths and patterns. By adjusting which layers are masked and which are exposed, the process can precisely control via formation and landing area creation, managing complexity through parameter variation rather than structural complexity.
3Ease of manufacture
If uniform etching is applied to all insulating and active layers, then the process is simpler, but etching depth issues arise due to varying material properties and thicknesses
Solution Approach 1:
The patent applies local quality by using etch masks to create spatially varying etching conditions. Different insulating layers receive different treatments - some are masked and protected, others are exposed and etched. This local differentiation solves the etching depth uniformity problem by allowing each layer to be etched to its appropriate depth based on its specific material properties and thickness, while maintaining overall process simplicity through the systematic use of masks.
Data Source
AI summary
A method for forming a contact structure includes forming a stack of alternating active layers and insulating layers. The stack includes first and second sub stacks each with active layers separated by insulating layers. The active layers of each sub stack include an upper boundary active layer. A sub stack insulating layer is formed between the first and second sub stacks with an etching time different from the etching times of the insulating layers for a given etching process. The upper boundary active layers are accessed, after which the remainder of the active layers are accessed to create a stairstep structure of landing areas on the active layers. Interlayer conductors are formed to extend to the landing areas, the interlayer conductors separated from one another by insulating material.