Stairstep Interposer Stack for TSV-Free Die Integration
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in integrating multiple semiconductor dice efficiently due to the limitations of structures like through silicon vias (TSVs), which are not viable in all cases.
Innovation Solution
A semiconductor package design that utilizes interposer layers stacked via solder bumps to create a stairstep structure, allowing multiple semiconductor dice to be stacked vertically with electrical connections maintained through the interposer stack, eliminating the need for wire bonds or TSVs, and encapsulated with a polymer composite for protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through silicon vias (TSVs) are used to integrate multiple semiconductor dice, then vertical electrical connections are achieved, but manufacturing complexity and applicability are limited
Solution Approach 1:
The patent introduces an interposer structure as an intermediary component between the substrate and semiconductor dice. The interposer includes a first interposer layer with a first via structure and a second interposer layer with a second via structure, which together provide vertical electrical connections without requiring TSVs through the semiconductor die itself. This mediator approach simplifies manufacturing by moving the complex via structures to the interposer layer where they are easier to fabricate.
Solution Approach 2:
The interposer is segmented into multiple layers (first interposer layer and second interposer layer) with distinct via structures at different levels. The first via structure extends through the first interposer layer while the second via structure extends through the second interposer layer, allowing independent optimization of each layer's manufacturing process and reducing overall complexity.
2Volume of moving object
If multiple semiconductor dice are stacked vertically, then space utilization is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent transitions from planar integration to three-dimensional vertical stacking by introducing multiple interposer layers and via structures that extend in the vertical dimension. The first via structure and second via structure are positioned at different heights and connect to different semiconductor dice, enabling efficient use of vertical space while maintaining manufacturability through the modular interposer design.
3Adaptability or versatility
If interposer layers are stacked to form stairstep structure, then applicability is improved for packages without TSVs, but structural complexity increases
Solution Approach 1:
The interposer structure employs local quality variations through the stairstep configuration, where the first interposer layer and second interposer layer have different horizontal positions creating stepped surfaces. Each via structure is locally optimized for its specific function: the first via structure connects to the first semiconductor die while the second via structure connects to the second semiconductor die at a different elevation, providing adaptable connectivity without uniform complexity throughout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances manufacturing efficiency and applicability by simplifying the process, maintaining electrical connections, and providing structural support and environmental protection for the semiconductor dice.
Implementation Method 1
attaching a first interposer layer on the package base via solder bumps; attaching a second interposer layer on the first interposer layer via solder bumps
Data Source
AI summary
A method for making a semiconductor device is provided. The method includes providing a package base; attaching a first interposer layer on the package base via solder bumps; attaching a first semiconductor die on the package base and adjacent to the first interposer layer; attaching a second interposer layer on the first interposer layer via solder bumps to form an interposer stack, wherein the first interposer layer and the second interposer layer define a step structure, wherein the step structure comprises two step surfaces extending from the first interposer layer and the second interposer layer on the side of the interposer stack, respectively; attaching a second semiconductor die on both of the first semiconductor die and the first interposer layer; and forming a first encapsulant layer on the package base to encapsulate the first interposer layer, the second interposer layer, the first semiconductor die, and the second semiconductor die.