Stall Logic for Data Processing Engine Cores

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Solution Overview

Problem

In integrated circuits, data transfer between cores is inefficient due to latency caused by core-to-core interfaces, which leads to suboptimal memory usage.

Innovation Solution

A data processing engine (DPE) array in an integrated circuit includes a core, memory, and support circuitry with a stall circuit that can stall or resume operations in response to inputs, allowing for direct memory access and hardware synchronization, thereby optimizing data transfer between cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is transferred between cores through core-to-core interface, then data transfer can be performed, but latency is added and memory usage becomes inefficient

Engineering Contradiction:

Improvedata transfer speedVSAvoidtransfer latency

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent introduces shared memory as an intermediary component between cores, allowing data to be stored in memory that is directly accessible by multiple cores without requiring core-to-core interface transfers. This mediator (shared memory) eliminates the latency associated with direct core-to-core communication while maintaining efficient data access.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system segments memory into separate data memory and program memory regions, with data memory being shared across multiple cores. This segmentation allows efficient organization of data access patterns and enables direct memory access (DMA) operations to optimize data transfer without involving the core-to-core interface.

Inventive Principle:

Principle #1Segmentation

2Productivity

If direct memory access is implemented, then memory usage efficiency improves, but synchronization complexity increases

Engineering Contradiction:

Improvememory usage efficiencyVSAvoidsynchronization complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms through status flags and control registers that monitor memory access states. When one core accesses shared data memory, status bits are set to indicate the access state, providing feedback to other cores and the DMA controller. This feedback system enables automatic synchronization without requiring complex manual coordination, maintaining high memory efficiency while managing synchronization complexity through automated status monitoring.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS10579559B1Stall logic for a data processing engine in an integrated circuit

Publication Date: 2020.03.03 XILINX INC

AI summary

An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes a core, a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory, and a stall circuit coupled to the core configured to stall or resume the core in response to one or more inputs.