Electronic Design Verification Using Stall Prevention Graph Analysis
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Solution Overview
Problem
Modern electronic circuit designs, such as SoC devices, face challenges in verifying whether subsystems operate as intended and detecting system-level deadlocks, which are often difficult to identify and resolve due to complex interactions and layering of interconnects and intellectual property blocks, requiring improved verification techniques.
Innovation Solution
A method for detecting system-level deadlocks using stall prevention requirements in electronic circuit models, involving identifying blocks, determining dependencies, constructing graphs, and performing loop analyses to identify potential deadlocks, while also eliminating false deadlocks to improve verification efficiency and effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional verification methods are used to verify subsystems and detect deadlocks in complex electronic circuit designs, then verification coverage can be achieved, but verification time and computational resources increase significantly
Solution Approach 1:
The patent segments the verification process into two distinct phases: (1) constructing a static dependency graph that captures all potential deadlock scenarios without execution, and (2) performing loop analysis on the graph to detect actual deadlocks. This segmentation allows the system to pre-compute dependencies once and reuse them across multiple verification scenarios, dramatically reducing verification time while maintaining comprehensive coverage of complex SoC designs with multiple interconnects and IP blocks.
Solution Approach 2:
The patent performs preliminary action by constructing the dependency graph beforehand, capturing all possible interactions between blocks, interconnects, and protocols before actual verification execution. The graph encodes stall prevention requirements and resource dependencies in advance, enabling the verification engine to quickly query pre-computed information rather than analyzing entire transaction flows during verification, thus reducing runtime significantly.
2Measurement precision
If detailed analysis of all blocks and interconnects is performed to detect system-level deadlocks, then detection accuracy improves, but computational complexity and resource requirements increase
Solution Approach 1:
The patent introduces a dependency graph as an intermediary data structure that mediates between the complex hardware architecture (blocks, interconnects, protocols) and the verification engine. The graph abstracts detailed hardware interactions into standardized nodes (representing blocks) and edges (representing resource dependencies and stall conditions), enabling the verification system to analyze complex SoC designs with high accuracy without being overwhelmed by implementation details.
Solution Approach 2:
The patent transforms the verification problem from analyzing concrete transaction flows with specific data values to analyzing abstract dependency relationships represented as graph structures. By changing the parameter representation from detailed transaction sequences to symbolic dependency edges with stall prevention requirements, the system achieves high detection accuracy while reducing computational complexity through graph theory algorithms.
3Ease of manufacture
If conventional verification approaches are used without structured analysis, then implementation is simpler, but false deadlocks cannot be eliminated and verification effectiveness decreases
Solution Approach 1:
The patent implements feedback through the loop analysis mechanism that systematically examines cycles in the dependency graph. When a potential deadlock is detected, the system traces back through the graph edges to identify the specific sequence of stall conditions and resource dependencies that created the cycle, providing feedback about the root cause. This structured feedback mechanism enables automatic elimination of false deadlocks by distinguishing between genuine resource conflicts and spurious detection artifacts, significantly improving verification effectiveness.
Data Source
AI summary
Various mechanisms and approaches identify multiple cells in an electronic design and multiple sets of stall prevention requirements or multiple sets of transactions for the multiple cells and determine dependencies between stall prevention requirements. A graph is constructed to represent the dependencies and the stall prevention requirements or the transactions involved in the dependencies by using the stall prevention requirements or the transactions as the nodes and the dependencies as the arcs connecting the nodes in the graph. One or more loop analyses are performed on the graph to identify one or more loops as one or more potential deadlocks. False deadlocks may be eliminated from further processing. The analyses and deadlock detection may be independently performed for each cell in sequence or in parallel to divide and conquer a complex electronic system design.