Stalling Synchronisation Circuits for Late Data Signals
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Solution Overview
Problem
Digital systems face inefficiencies due to the need for large safety margins in clock frequency and operational voltage to account for worst-case scenarios, leading to power and performance waste, and existing error correction methods incur overheads by reissuing instructions.
Innovation Solution
A data processing circuitry with synchronization circuits grouped to detect unstable input signals and propagate a stall signal, adding a one-clock cycle delay to ensure data stability without reissuing instructions, allowing for reduced margins and improved efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large safety margins are introduced in clock frequency and operational voltage to account for worst-case scenarios, then data stability and reliability are improved, but power consumption and performance are worsened
Solution Approach 1:
The system performs preliminary detection of data stability during a predetermined time window before the sampling edge. By detecting whether data is stable in advance, the system can take preliminary corrective action (stalling) if needed, rather than relying on large safety margins to prevent errors from occurring in the first place.
Solution Approach 2:
The system implements feedback by monitoring data stability during the predetermined time and using this information to control the sampling process. If data is detected as unstable, a stall signal is generated to delay sampling until stable data is available, creating a closed-loop system that adapts to actual data conditions rather than relying on fixed safety margins.
2Reliability
If large safety margins are introduced in clock frequency and operational voltage to account for worst-case scenarios, then data stability and reliability are improved, but performance is worsened
Solution Approach 1:
The system performs preliminary detection of data stability during a predetermined time window before the sampling edge. By detecting whether data is stable in advance, the system can take preliminary corrective action (stalling) if needed, rather than relying on large safety margins to prevent errors from occurring in the first place.
Solution Approach 2:
The system dynamically adjusts the sampling timing based on actual data stability conditions. Instead of using fixed safety margins that reduce performance, the system can stall for one clock cycle when data is unstable and proceed normally when data is stable, making the system adaptive and performance-optimized under varying conditions.
3Reliability
If error detection and recovery means are added to correct timing errors, then reliability is improved, but device complexity and overhead are worsened
Solution Approach 1:
The system uses self-service by having the data processing circuitry itself monitor its own data stability and generate stall signals to correct timing errors. Rather than adding complex external error correction hardware, the system leverages existing components (data inputs, timing circuits, and control logic) to perform error detection and correction, minimizing additional complexity.
Solution Approach 2:
The system extracts the error detection and correction function from complex architectural changes and implements it through a simple stall mechanism. By separating the correction function into a simple one-clock-cycle stall operation rather than integrating it into the entire data processing architecture, the system reduces overall complexity while maintaining reliability.
4Reliability
If error correction involves reissuing instructions, then data integrity is improved, but loss of time and productivity are worsened
Solution Approach 1:
The system extracts the correction function from complex instruction reissuing operations and implements it through a simple stall mechanism. By separating the correction function into a simple one-clock-cycle stall operation rather than integrating it into the entire data processing architecture, the system reduces overall complexity while maintaining reliability.
Solution Approach 2:
The system skips the complex process of reissuing instructions by using a direct stall mechanism that simply delays the sampling operation for one clock cycle. This rushing through of the correction process eliminates the time-consuming instruction reissue steps while still ensuring data integrity is restored.
Data Source
AI summary
A data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a plurality of synchronization circuits for capturing and transmitting the data in response to a clock signal and a plurality of combinational circuits arranged between the synchronization circuits for processing the data, the plurality of synchronization circuits being arranged in at least two groups; an error detecting circuit for determining if the data input to one of the plurality of synchronization circuits is stable during a predetermined time and for signalling an error if the data input is unstable, the predetermined time being less than a half cycle of the clock signal; control circuitry responsive to said error detecting circuit signalling said error to transmit a control signal to at least one of said groups of synchronization circuits that contains a subsequent synchronization circuit that said synchronization circuit with said unstable input is configured to transmit said data to; each of said group of synchronization circuits being configured to respond to receipt of said control signal to stall for a clock cycle and to transmit a stall signal to at least one further group of synchronization circuits that said group of synchronization circuits is configured to transmit data to or receive data from; each of said group of synchronization circuits being configured to respond to receipt of said stall signal provided they have not stalled in a preceding clock cycle to stall for a clock cycle and to transmit a stall signal to said at least one further group of synchronization circuits.