Stampable NoC Partitions for Scalable Post-Fabrication Routing
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Solution Overview
Problem
Existing network-on-chip (NOC) architectures face limitations in scalability and design time due to the need for custom creation of each network partition, hindering efficient design of large and complex system-on-chips.
Innovation Solution
A network-on-chip architecture utilizing stampable partitions with pre-built communication links and configuration bus nodes, allowing for post-fabrication configuration and efficient design through replication of pre-designed units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If custom creation of each network partition is performed, then design flexibility is improved, but design time and effort increase significantly
Solution Approach 1:
The network-on-chip is divided into multiple stampable partitions, each containing routers and pre-built communication links. This segmentation allows the network to be broken down into reusable modular units that can be instantiated multiple times, reducing overall design time while maintaining flexibility through configuration options.
Solution Approach 2:
Pre-designed stampable partition templates are created and then instantiated multiple times throughout the network-on-chip design. These templates can be copied and reused across different partitions, significantly reducing repetitive design effort while allowing customization through configuration parameters such as router counts and link arrangements.
2Adaptability or versatility
If network-on-chip architecture is designed for large scale, then scalability is improved, but design complexity increases
Solution Approach 1:
The large-scale network-on-chip is segmented into multiple manageable stampable partitions, each with a standardized structure containing routers and pre-built communication links. This segmentation reduces design complexity by breaking down the large system into smaller, more manageable units that follow a consistent template, making the overall design process more tractable.
Solution Approach 2:
The stampable partition template is designed to be universal and multi-functional, capable of being instantiated in various configurations to meet different design requirements. The template can accommodate different numbers of routers, various link arrangements, and multiple partition types, allowing a single design to scale across diverse application scenarios without increasing complexity.
3Manufacturing precision
If fixed network partition design is used, then manufacturing precision is improved, but adaptability for different applications decreases
Solution Approach 1:
The stampable partition design incorporates dynamic configurability through configuration registers that can be programmed after fabrication. While the physical structure of each partition is fixed and precise, the logical configuration (such as router assignments, link activations, and partition identifiers) can be dynamically adjusted through register programming, enabling post-fabrication adaptation to different applications.
Solution Approach 2:
The invention enables parameter changes in the network-on-chip configuration through programmable registers within each stampable partition. By changing parameters stored in these registers (such as routing tables, partition IDs, and link configurations), the same physical hardware can be reconfigured for different applications, maintaining manufacturing precision while achieving adaptability.
Data Source
AI summary
The present invention relates to a network-on-chip architecture (100), characterized by: a plurality of stampable partition (200), each partition including one or more router (10) adapted for communication, registers and pre-built communication links established in cardinal directions or other directions, and one or more configuration bus node (20) deposited in each partition (200) connecting to the registers (40); a system integrator connecting a system operator (60) to one of the configuration bus node (20); wherein the system operator (60) initializes a path mapping between the configuration bus node (20) forming a secondary configuration network and access the registers (40) in each partition to program the registers (40) with routing data A method of processing data at the network-on-chip architecture (100) is also disclosed herein.