Standalone Mode for Independent Die Testing

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Solution Overview

Problem

The existing interconnected die architecture in memory devices makes it costly and challenging to test and debug individual dies before integration, leading to potential delays and inefficiencies in the manufacturing process.

Innovation Solution

A standalone mode is introduced, allowing individual dies to operate independently prior to integration, enabling testing and debugging at earlier stages, such as the wafer level or single-die-package level, using a configuration where interface and linked dies can perform standalone read and write operations without being connected.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If individual dies are tested after integration into interconnected die architecture, then testing can be performed on complete system, but testing cost and complexity increase significantly

Engineering Contradiction:
Improvetesting effectivenessVSAvoidtesting complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the testing process into two independent stages: (1) standalone die-level testing before integration, and (2) integrated system testing after assembly. The standalone mode enables individual dies to be tested independently using simplified test interfaces, separating the complex integrated system test into manageable die-level tests that can be performed earlier in the manufacturing process.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent enables preliminary testing of individual dies at the wafer level or single-die-package level before they are integrated into the interconnected die architecture. This preliminary action allows defects to be identified and eliminated early in the manufacturing process, avoiding the need for complex rework after integration.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If standalone mode is implemented for individual dies, then testing efficiency improves, but additional circuitry and control mechanisms are required

Engineering Contradiction:
Improvetesting efficiencyVSAvoidcircuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent designs the test interface circuitry to serve dual purposes: (1) standalone die-level testing in isolation mode, and (2) integrated system testing in interconnected mode. The same basic test interface and control logic can operate in both standalone and integrated configurations, reducing the need for entirely separate testing infrastructure.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent extracts the essential testing functionality from the complex integrated system and implements it at the die level. By taking out the core test interface and control mechanisms and placing them at the individual die level, the system enables efficient standalone testing without requiring the full integrated system to be assembled and operational.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If testing is performed at wafer level or single-die-package level, then manufacturing cost decreases, but testing capabilities must be simplified

Engineering Contradiction:
Improvemanufacturing costVSAvoidtesting capability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the testing capability into essential functions that can be performed at the die level using simplified interfaces. Rather than attempting to perform all possible system-level tests at the wafer level, the invention focuses on implementing the core testing functions that are sufficient to identify major defects early in manufacturing, accepting that more comprehensive testing will occur after integration.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12100468B2Standalone mode
Publication Date: 2024.09.24 MICRON TECHNOLOGY INC
  • US12100468B2 patent drawing
  • US12100468B2 patent drawing
  • US12100468B2 patent drawing

AI summary

Apparatuses and techniques for implementing a standalone mode are described. The standalone mode refers to a mode in which a die that is designed to operate as one of multiple dies that are interconnected can operate independently of another one of the multiple dies. Prior to connecting the die to the other die, the die can perform a standalone read operation and/or a standalone write operation in accordance with the standalone mode. In this way, testing (or debugging) can be performed during an earlier stage in the manufacturing process before integrating the die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die-package (SDP) level. In general, the standalone mode can be executed independent of whether the die is connected to the other die.