Standalone MTJ Array Sensing Without Peripheral Bias Circuitry
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Solution Overview
Problem
Integrated circuit memory devices, particularly magnetoresistive tunnel junctions (MTJs), are prone to defects such as shorts or opens during manufacturing or throughout their lifetime, affecting performance and requiring peripheral bias circuitry for operation.
Innovation Solution
A memory device that tolerates defects by using an MTJ array with multiple MTJs connected in series, parallel, or a combination, and a read device without bias circuitry, employing a strong arm latch to sense the logical state based on differential resistance without requiring complex timing sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If peripheral bias circuitry is used to operate MTJs, then MTJ operation is enabled, but device complexity increases and defect tolerance is reduced
Solution Approach 1:
The patent extracts and eliminates the peripheral bias circuitry from the memory device architecture. By using an array of MTJs with differential resistance characteristics, the device can sense logical states without requiring external bias circuitry, thereby reducing device complexity while maintaining operation capability.
Solution Approach 2:
The MTJ array is designed to perform multiple functions: storing data, sensing logical states, and providing defect tolerance all within the same structure. The differential resistance property of the MTJ array enables it to function as both memory storage and sensing mechanism, eliminating the need for separate bias circuitry.
2Reliability
If MTJ array with multiple MTJs is used, then defect tolerance is improved, but device area increases
Solution Approach 1:
The patent segments the memory function into multiple MTJs arranged in an array configuration. Each MTJ contributes to the overall differential resistance characteristic, and the segmented structure provides defect tolerance because a single defect does not determine the state of the entire array. This segmentation allows defect tolerance without requiring excessive area.
Solution Approach 2:
The patent combines multiple MTJs into a unified array structure that shares common sensing circuitry. By merging the sensing function across multiple MTJs, the design achieves defect tolerance while minimizing the area overhead compared to having separate sensing circuits for each MTJ.
3Ease of operation
If strong arm latch is used for sensing, then reading operation is simplified, but timing control complexity increases
Solution Approach 1:
The strong arm latch circuit is designed to automatically sense and latch the differential resistance state of the MTJ array without requiring complex external timing control. The latch circuit self-regulates the sensing operation, eliminating the need for precise timing sequences and simplifying the reading operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables seamless reading of MTJ states despite defects, minimizing read disturb exposure and eliminating the need for peripheral bias circuitry, allowing the device to function as a standalone bitcell on an integrated circuit.
Implementation Method 1
a magnetic tunnel junction (MTJ) array having a logical state, the MTJ array including a first set of one or more MTJs and a second set of one or more MTJs
Data Source
AI summary
A memory device includes a magnetic tunnel junction (MTJ) array having a logical state and a capacitive net charged to a first voltage and electrically connected to the MTJ array. The memory device further includes a read device electrically connected to the MTJ array and configured to read the logical state of the MTJ array as the capacitive net discharges to a second voltage different than the first voltage.