Standard Cell Architecture With Asymmetric Wrapped Channels
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Solution Overview
Problem
The decreasing cell heights in semiconductor devices lead to increased cell density, necessitating improvements in cell architecture to enhance density and performance.
Innovation Solution
Implementing a standard cell architecture with four metal tracks in a first metal layer, utilizing self-aligned quadruple patterning (SAQP) to create either uniform or asymmetric distributions of wrapped channels, combining fins or using asymmetric nanosheets, and incorporating a single bar via for inter-layer connections to reduce cell height and increase transistor density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cell height is decreased to increase cell density, then cell density is improved, but manufacturing precision and performance uniformity deteriorate
Solution Approach 1:
The patent applies asymmetry by implementing non-uniform pitch distribution among wrapped channels. Specifically, different wrapped channels have different pitch values (e.g., first pitch, second pitch, third pitch), creating asymmetric spacing patterns. This asymmetric design allows optimization of transistor performance and electrical characteristics while maintaining high cell density, resolving the contradiction between increased density and maintained performance uniformity.
2Quantity of substance
If more wrapped channels are integrated into each cell, then transistor density is improved, but cell architecture complexity increases
Solution Approach 1:
The patent implements local quality by assigning different pitch characteristics to different wrapped channels within the same cell. Each wrapped channel can have optimized pitch values tailored to its specific electrical requirements and position. This localized optimization approach enables high transistor density while managing architecture complexity through systematic variation rather than uniform design.
Solution Approach 2:
The patent achieves multi-functionality by using the same wrapped channel structure and formation process across different cells, but varying the pitch parameters to achieve different performance characteristics. This universal approach with parameter variation allows the same basic architecture to serve multiple functions and performance requirements, increasing transistor density without proportionally increasing overall system complexity.
3Ease of manufacture
If uniform pitch is used among wrapped channels, then manufacturing simplicity is improved, but performance optimization capability deteriorates
Solution Approach 1:
The patent applies parameter changes by varying the pitch parameter across different wrapped channels. Instead of using a single uniform pitch value, the design incorporates multiple pitch values (first pitch, second pitch, third pitch) that can be optimized for different performance requirements. This parameter variation enables performance optimization while maintaining manufacturability through systematic pitch control in the patterning process.
Data Source
AI summary
In a first aspect, a semiconductor device includes a plurality of cells. Each cell of the plurality of cells includes four metal tracks running substantially parallel to each other in a first metal layer to provide signal routing and a plurality of wrapped channels having a pitch that is uniform among the plurality of wrapped channels. In a second aspect, a semiconductor device includes a plurality of cells. Each cell of the plurality of cells includes four metal tracks running substantially parallel to each other in a first metal layer to provide signal routing and a plurality of wrapped channels having an asymmetric distribution. For example, a first distance between a first pair of adjacent wrapped channels is different than a second distance between a second pair of adjacent wrapped channels.