Standard Cell Layout With Backside Power Delivery
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Solution Overview
Problem
Conventional standard cell designs require space allocation for power delivery, which increases the device footprint and leads to higher power consumption and voltage drop due to tight metal pitches and backside power delivery methods consuming valuable real-estate.
Innovation Solution
A standard cell architecture is designed without front-side power delivery tracks or boundary deep vias, utilizing back-side power delivery and minimizing the distance between transistors to optimize area and signal routing, while maintaining robust power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power delivery space is allocated on the front side metal routing layers and diffusion placement, then power delivery can be provided through front side bump or wafer backside metals, but the overall footprint of the device increases
Solution Approach 1:
The patent moves power delivery from the traditional front-side planar dimension to the vertical dimension by implementing backside power delivery through the substrate. Power is delivered through the backside of the semiconductor substrate to the active devices, eliminating the need for front-side power routing space and reducing the device footprint.
Solution Approach 2:
The patent extracts the power delivery function from the front-side metal routing layers and diffusion placement, separating it into a dedicated backside power delivery path. This extraction allows the front side to be used entirely for signal routing and functional devices, while power delivery is handled independently through the substrate backside.
2Reliability
If power delivery is provided through front side bump to the first metal routing layer, then power can be delivered to the device, but the metal pitch becomes tight and resistance increases
Solution Approach 1:
The patent transitions power delivery from the front-side metal routing plane to the vertical substrate path. By delivering power through the backside of the substrate directly to the active devices, the current path is shortened and metal pitch is relaxed, reducing resistive losses and power consumption.
3Reliability
If space is allocated for power delivery on the front side, then power delivery infrastructure is established, but the density of functional units on the chip decreases
Solution Approach 1:
The patent relocates power delivery to the vertical dimension through backside substrate delivery, freeing up the front-side planar space. This allows maximum packing of functional units (transistors, memory cells, etc.) on the chip front side, thereby increasing integration density while maintaining robust power delivery through the substrate backside.
Data Source
AI summary
Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to standard cell architectures without power delivery space allocation. Other embodiments may be described or claimed.