Standard Cell Contact Structure for Dense IC Layout Alignment
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Solution Overview
Problem
The existing integrated circuit (IC) design using standard cells results in increased area due to reserved spaces and misalignment issues with conductive features, leading to performance degradation and yield reduction.
Innovation Solution
The proposed IC structure incorporates standard cells with filler cells and optimized interconnect structures, including dielectric gates and multiple-layer contacts, to enhance packing density and performance by ensuring proper isolation and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If standard cells are placed close to each other to reduce area, then area usage is improved, but active regions cannot be joined and require additional metal lines, degrading performance
Solution Approach 1:
The patent introduces a vertical dimension by forming contact structures that extend through the substrate to connect active regions between adjacent standard cells. Instead of using horizontal metal lines to connect spaced-apart active regions, the invention creates vertical pathways through the substrate, allowing active regions to be electrically coupled without increasing horizontal spacing between cells.
2Reliability
If conductive features are designed with greater dimensions to ensure proper contact, then contact reliability is improved, but misalignment causes short issues
Solution Approach 1:
The patent implements different contact structure configurations at different locations within the standard cell. Contact structures are selectively formed depending on whether they are adjacent to other contact structures or isolated, with dimensions and spacing adjusted locally to prevent shorts while ensuring proper contact. This localized optimization allows reliable electrical connection without creating short circuit hazards.
3Object-generated harmful factors
If conductive features are designed with less dimensions to avoid short issues, then short risk is reduced, but contact resistance increases and open issues occur
Solution Approach 1:
The patent creates a nested contact structure where a first contact structure is formed within a second contact structure. This nested configuration allows smaller contact features to be positioned precisely within larger contact areas, ensuring low contact resistance while maintaining compact dimensions that avoid short circuit issues. The nested arrangement provides both the electrical connectivity of large contacts and the spatial efficiency of small contacts.
4Manufacturing precision
If filler cells are added between standard cells to improve isolation and alignment, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent designs filler cells that serve multiple functions simultaneously: they provide mechanical support for alignment during fabrication, create isolation regions between adjacent standard cells, and establish reference structures for contact structure formation. By combining these functions into a single structural element, the invention improves manufacturing precision without proportionally increasing device complexity.
Data Source
AI summary
An IC structure includes a first standard cell having a first pFET and a first nFET integrated; a first, second and third gates longitudinally oriented along a first direction and configured in the first standard cell; a first gate contact landing on the first gate and being adjacent two S/D contacts on two opposite edges of the first gate; a second gate contact landing on the second gate and being adjacent a single S/D contact on one edge of the second gate; and a third gate contact landing on the third gate and being free from any S/D contact. The first, second and third gate contacts span a first dimension D1, a second dimension D2, and a third dimension D3, respectively, along a second direction being orthogonal to the first direction. D1 is less than D2 and D2 is less than D3.