Standard Cell Layout Using Cutting Layers to Ease Routing Congestion
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Solution Overview
Problem
Integrated circuits face challenges with increased integration density, leading to routing congestion and inefficient use of area, which affects performance and turn around time (TAT).
Innovation Solution
A layout design method for integrated circuits that involves placing standard cells adjacent to each other based on connection relationships, using cutting layers to insulate non-interconnected cells, and optimizing the placement of contact layers to reduce congestion and optimize area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If integration density of integrated circuits is increased to meet demands for higher performance and multi-functionality, then the functionality and performance of integrated circuits are improved, but routing congestion increases and area optimization becomes more difficult
Solution Approach 1:
The patent segments the contact layer into multiple cutting layers (first cutting layer, second cutting layer, third cutting layer) that are positioned at different locations and orientations. This segmentation allows independent control of routing paths in different regions, reducing routing congestion while maintaining high integration density. Each cutting layer can be independently optimized for specific routing requirements.
Solution Approach 2:
The patent introduces multiple cutting layers at different vertical positions and orientations (first cutting layer extending in first direction, second cutting layer extending in second direction perpendicular to first direction, third cutting layer extending in third direction perpendicular to second direction). This multi-dimensional approach to routing allows signals to switch between different layers and directions, effectively reducing congestion in any single plane while maintaining high functionality.
2Productivity
If integration density is increased, then more functions can be integrated, but area optimization becomes more difficult and routing becomes more congested
Solution Approach 1:
The contact layer is divided into multiple cutting layers that can be independently positioned and sized. This segmentation allows each cutting layer to be optimized for its specific routing function, minimizing the area required for each layer while collectively achieving high integration density. The first, second, and third cutting layers can be placed in different regions, optimizing area utilization.
Solution Approach 2:
By distributing routing functions across multiple cutting layers in different directions and positions, the patent achieves high integration density without proportionally increasing the overall area. The multi-layer approach allows efficient packing of routing paths in three-dimensional space, optimizing area utilization while supporting high integration density.
3Productivity
If standard cells are placed adjacent to each other based on connection relationships, then routing efficiency is improved, but turn around time (TAT) must be minimized
Solution Approach 1:
The patent performs preliminary placement of standard cells based on connection relationships before final routing. By pre-positioning cells that are connected to each other, the routing process requires fewer adjustments and iterations, improving routing efficiency while minimizing the time lost in iterative optimization. The cutting layers are also pre-positioned to facilitate efficient routing.
4Device complexity
If cutting layers are used to insulate non-interconnected cells, then routing congestion is reduced, but manufacturing complexity increases
Solution Approach 1:
The contact layer is segmented into multiple cutting layers that can be independently manufactured and positioned. Each cutting layer serves a specific insulation function for non-interconnected cells, reducing routing congestion by providing clear separation. The segmented structure allows each layer to be optimized for its specific manufacturing process, potentially simplifying overall manufacturing despite the multi-layer structure.
Solution Approach 2:
The patent uses cutting layers extending in multiple directions (first direction, second direction perpendicular to first, third direction perpendicular to second) to provide insulation in three-dimensional space. This multi-dimensional insulation approach reduces routing congestion by preventing unwanted connections in all directions, while the systematic arrangement of layers follows manufacturing best practices.
Data Source
AI summary
Example embodiments provide a layout design method for an integrated circuit including obtaining a connection relationship of multiple standard cells, placing a first standard cell of the plurality of standard cells and a second standard cell of the plurality of standard cells adjacent to each other in a first direction based on the connection relationship between the first standard cell and the second standard cell, and placing a cutting layer for a contact layer between the first standard cell and a third standard cell of the plurality of standard cells arranged adjacent to the first standard cell in the first direction based on the connection relationship between the first standard cell and the second standard cell.