Standard Cell Libraries With Defect Injection for Yield Prediction
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Solution Overview
Problem
Existing Electronic Design Automation (EDA) tools face challenges in accurately predicting standard cell yield and performance due to inherent issues in third-party libraries that are not discovered until the product is fabricated, leading to potential manufacturing defects and low yield in complex integrated circuits.
Innovation Solution
Implementing machine learning (ML) and artificial intelligence (AI) to provide defect-aware libraries that analyze geometric defects in standard cells, simulate yield, and generate inferred failure rates, using geometric analysis and defect injection processes to predict yield and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If third-party libraries are used for standard cell performance characteristics, then design efficiency is improved, but manufacturing yield deteriorates due to undetected process issues
Solution Approach 1:
The patent applies preliminary action by performing geometric analysis and defect injection simulations on standard cell libraries during the design phase, before actual manufacturing. This allows potential defects to be identified and characterized in advance, enabling designers to adjust their designs proactively rather than discovering issues during fabrication and testing.
Solution Approach 2:
The patent introduces an intermediary defect injection process that acts as a mediator between the design phase and manufacturing phase. By injecting simulated defects into the library during design validation, the system creates a bridge that allows manufacturing issues to be detected and addressed before production, resolving the contradiction between using third-party libraries and ensuring manufacturing yield.
2Reliability
If geometric analysis and defect injection processes are implemented, then manufacturing yield is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by enabling the standard cell library to analyze and characterize its own geometric properties and potential defects through automated geometric analysis tools. The library performs self-validation through defect injection processes, eliminating the need for external manual analysis and reducing overall system complexity despite adding analytical capabilities.
Solution Approach 2:
The patent changes parameters by transforming the standard cell library from a static performance characteristic repository to a dynamic model that includes geometric analysis results and defect injection data. This parameter transformation adds yield prediction capabilities without requiring fundamentally new processes, as it builds upon existing library structures with enhanced analytical parameters.
3Manufacturing precision
If defect-aware libraries are used, then manufacturing precision is improved, but loss of information increases due to additional analysis requirements
Solution Approach 1:
The patent extracts only the critical geometric parameters and defect characteristics needed for yield prediction from the comprehensive standard cell library data. By selecting and analyzing only the most relevant geometric features and defect modes, the system achieves high manufacturing precision without processing unnecessary information, thus minimizing data overhead while maximizing yield prediction accuracy.
Data Source
AI summary
Systems and methods for providing standard cell yield information in a library (i.e., creating “defect-aware” libraries). The method includes accessing a library of a plurality of standard cells characterized on a foundry process node and revision. A geometric analysis is performed on individual ones of the standard cells to identify potential defects, such as shorts and opens. A defect is injected (i.e., “realized” or “actualized”) at the location of the identified potential defects. The standard cells in the library are then simulated with the defects injected to generate simulated yield information. Additionally, methods can access silicon failure analysis data representing test chips designed with the library and generate an inferred failure rate for the individual standard cells in the library, as a function of the silicon failure analysis and the simulated yield information.