Standard Cell Design Reducing Worst Path Delay
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Solution Overview
Problem
In advanced technology nodes, parasitic capacitances and resistances degrade the performance of multi-input standard cells, leading to increased cell delay and reduced usage in high-speed digital blocks, as existing standard cells are limited by worst path delay.
Innovation Solution
The design of a standard cell incorporating specific configurations of PMOS and NMOS transistors, where the gate terminals receive inputs and drain terminals are coupled to form nodes, with parasitic capacitances and load capacitances managed to reduce worst path delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multi-input standard cells are used to achieve area efficiency, then area utilization is improved, but cell delay increases due to parasitic capacitances and resistances
Solution Approach 1:
The multi-input standard cell is segmented into multiple independent two-input NAND gate paths. Each input has its own dedicated path through the transistor network, preventing the accumulation of parasitic effects that would occur in a single long path. This segmentation maintains area efficiency while reducing the effective delay by creating parallel, shorter signal paths.
Solution Approach 2:
Different regions of the standard cell are designed with optimized transistor sizing and connectivity to locally minimize parasitic effects. The transistor widths and lengths are adjusted in specific areas to balance drive strength against parasitic capacitance, ensuring that each local region contributes optimally to reducing overall cell delay while maintaining compact area.
2Speed
If transistor sizing is increased to reduce delay, then speed is improved, but parasitic capacitances increase
Solution Approach 1:
The invention optimizes transistor parameters (width, length, positioning) to achieve the desired speed performance while controlling parasitic capacitances. By carefully adjusting these parameters in the transistor model, the design achieves faster switching speeds without proportionally increasing parasitic effects, as the parameters are tuned to balance performance and parasitic constraints.
Solution Approach 2:
Rather than uniformly increasing all transistor sizes to reduce delay, the invention applies partial sizing optimization only where necessary in the critical paths. This selective approach achieves the required speed improvement while avoiding excessive parasitic capacitance increases in non-critical regions, maintaining a better overall balance between performance and parasitics.
Data Source
AI summary
The disclosure provides a standard cell. The standard cell includes a first PMOS transistor and a second PMOS transistor whose gate terminal respectively receives a first input and a second input. A drain terminal of each of the first PMOS transistor and the second PMOS transistor is coupled to a first node. The standard cell further includes a first NMOS transistor and a third NMOS transistor whose gate terminal respectively receive the first input and the second input. A drain terminal of each of the first NMOS transistor and the third NMOS transistor is coupled to the first node. The first NMOS transistor is coupled to a second NMOS transistor, and the third NMOS transistor is coupled to a fourth NMOS transistor. A gate terminal of the second NMOS transistor and the fourth NMOS transistor respectively receives the second input and the first input.