Standard Cell Layout With Direct M2 Routing and Reduced PMOS-NMOS Gap
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Solution Overview
Problem
Conventional standard cells face challenges in miniaturization as the size of transistors and metal connections increase due to interference among contacts and metal wires, leading to larger die sizes and latch-up issues, making it difficult to scale logic circuits effectively below 28 nm without increasing area size.
Innovation Solution
A new standard cell design with a compact layout style that includes transistors with fin structures and reduced gap distances between PMOS and NMOS transistors, allowing direct connections to Metal-2 layers without transitional Metal-1 layers, and utilizing selective epitaxy growth for precise control of transistor dimensions and reduced latch-up distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional standard cells use multiple interconnection layers (M1, M2, M3) with via connections, then signal transmission is facilitated, but the total area of the standard cell dramatically increases when minimum feature size decreases
Solution Approach 1:
The patent reconfigures the interconnection architecture by allowing gate contacts to connect directly to M2 layer, bypassing the traditional M1 intermediate layer. This dimensional reorganization in the interconnection stack reduces the horizontal space required for routing, thereby decreasing standard cell area while maintaining signal transmission capability.
Solution Approach 2:
The invention extracts the mandatory M1 layer connection from the gate contact path. By removing the requirement for gate contacts to traverse through M1, the design eliminates unnecessary via structures and reduces the overall footprint of the standard cell, particularly in the vertical direction where contacts are arranged.
2Quantity of substance
If minimum feature size is reduced to increase storage density, then transistor scaling is achieved, but the total area of standard cell increases due to contact and metal wire interference
Solution Approach 1:
The patent changes the interconnection architecture parameters by modifying the connection path from Gate-Con-M1-Via1-M2 to Gate-Con-M2. This parameter change in the interconnection topology allows for more efficient space utilization, enabling continued scaling of storage density without the area penalty that normally accompanies minimum feature size reduction.
3Ease of manufacture
If traditional interconnection structure is used with M1 layer connections, then manufacturing process is established, but wiring connections block efficient channeling and increase die size
Solution Approach 1:
The invention inverts the traditional interconnection hierarchy by allowing direct M2 access from gate contacts, reversing the conventional wisdom that M1 must be the first connection layer. This inversion enables more efficient wiring channeling and reduces die size while remaining compatible with existing manufacturing processes through selective contact formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new standard cell maintains a consistent area size across different technology nodes, reduces latch-up issues, and enables efficient scaling without increasing die size, allowing for smaller transistor dimensions and improved connectivity.
Implementation Method 1
utilizing selective epitaxy growth for precise control of transistor dimensions and reduced latch-up distances
Data Source
AI summary
A standard cell includes plural of transistors including a first type transistor and a second type transistor, plural of contacts coupled to the transistors; at least one input line electrically coupled to the transistors; an output line electrically coupled to the transistors; a VDD contacting line electrically coupled to the transistors; a VSS contacting line electrically coupled to the transistors; wherein the first type transistor includes a first set of fin structures electrically coupled together, the second type transistor includes a second set of fin structures electrically coupled together, and a gap between the first type transistor and the second type transistor is not greater than 3×Fp minus A, wherein Fp is a pitch distance between two adjacent fin structures in the first type transistor and A is a minimum feature size of the standard cell.