Standard Cell Layout With Edge MD Regions for Higher Gate Density
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Solution Overview
Problem
Existing integrated circuit (IC) layout designs face challenges in reducing cell width and increasing gate density, as traditional approaches result in wider cells when abutting cells with dummy gate regions, limiting the compactness and functionality of IC layouts.
Innovation Solution
The use of conductive regions, referred to as MD regions, on the edges of cells allows for direct abutment or insertion of filler cells, reducing cell width and enhancing gate density by merging MD regions and maintaining electrical connections, thereby enabling more compact IC layouts with increased functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional approaches with dummy gate regions are used, then electrical connections are maintained, but cell width increases and gate density decreases
Solution Approach 1:
The patent extracts and removes the dummy gate regions from the cell structure. By eliminating these non-functional regions that occupy space without providing electrical connection benefits, the cell width is reduced while maintaining the necessary electrical connections through the MD regions alone, thereby increasing gate density.
Solution Approach 2:
The patent merges the MD regions at the abutting edges of adjacent cells by removing dummy gate regions. This merging allows the conductive regions to directly connect across cell boundaries, eliminating the need for separate dummy gate structures and reducing overall cell width while maintaining electrical continuity.
2Area of moving object
If cells are abutted with dummy gate regions, then electrical connections are maintained, but cell compactness decreases
Solution Approach 1:
The patent extracts and removes dummy gate regions from the cell structure. By eliminating these non-functional regions that occupy space without providing electrical connection benefits, the cell width is reduced while maintaining the necessary electrical connections through the MD regions alone, thereby increasing gate density.
Solution Approach 2:
The patent merges the MD regions at the abutting edges of adjacent cells by removing dummy gate regions. This merging allows the conductive regions to directly connect across cell boundaries, eliminating the need for separate dummy gate structures and reducing overall cell width while maintaining electrical continuity.
Data Source
AI summary
A non-transitory computer-readable medium contains thereon a cell library. The cell library includes a plurality of cells configured to be placed in a layout diagram of an integrated circuit (IC). Each cell among the plurality of cells includes a first active region inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region overlaps the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region. The plurality of cells includes at least one cell a width of which in the first direction is equal to one gate region pitch between adjacent gate regions of the IC.