Standard Cell FET Layout for Low-Track-Height PN Separation
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Solution Overview
Problem
Reduced track height in semiconductor devices leads to challenges in maintaining pn separation between adjacent transistors, complicating gate formation and reducing drive current in nanosheet-based FETs.
Innovation Solution
A circuit cell design featuring two FET devices with common body portions arranged laterally opposite and gate prongs vertically offset, allowing for non-overlapping gate-to-source/drain configurations, eliminating pn separation along the height direction and facilitating independent gate formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If track height is reduced to improve area efficiency, then area efficiency is improved, but pn separation between adjacent transistors is reduced
Solution Approach 1:
The patent transitions from a planar arrangement where source/drain bodies are separated vertically in the track height direction to a three-dimensional arrangement where they are separated laterally at opposite sides of the routing track. The gate prongs extend vertically to overlap both source and drain regions, achieving pn separation through lateral and vertical positioning rather than vertical stacking, thus maintaining reduced track height while ensuring adequate pn separation for gate formation.
2Manufacturing precision
If pn separation is increased to facilitate gate formation, then gate formation is improved, but track height must be increased
Solution Approach 1:
The patent employs asymmetric positioning of the first and second source/drain bodies at opposite lateral sides of the routing track, with the gate body positioned asymmetrically to overlap both regions through vertically extending gate prongs. This asymmetric three-dimensional arrangement enables adequate pn separation for selective pWFM removal and gate formation without requiring increased track height, as the separation is achieved through lateral distribution and vertical gate extension rather than vertical stacking.
3Manufacturing precision
If channel width is reduced to increase pn separation, then pn separation is improved, but drive current is reduced
Solution Approach 1:
The patent achieves pn separation by distributing source and drain bodies laterally at opposite sides of the routing track and extending gate prongs vertically to overlap both regions, rather than reducing channel width. This three-dimensional arrangement maintains adequate pn separation for gate formation while preserving sufficient channel width to ensure adequate drive current performance.
Data Source
AI summary
A standard cell semiconductor device is provided that includes a first and second FET device, each including: (i) a source body and a drain body, each including a common source or drain body portion and a set of source or drain prongs protruding from the common source or drain body portion, (ii) a set of channel layers, each channel layer extending between a pair of source and drain prongs, and (iii) a gate body including a common gate body portion and a set of gate prongs protruding from the common gate body portion.