Standard Cell Gate Layout With Same-Layer Interconnect
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Solution Overview
Problem
Existing semiconductor structures fabricated using standard cell templates exhibit high power consumption and poor signal quality due to long electrical connection paths with high resistance and capacitance delay, leading to irregular circuit layouts and low design efficiency.
Innovation Solution
A standard cell template with a gate electrical connection pattern arranged on the same layer as the gates, eliminating the need for contact hole structures and reducing resistance, thereby shortening electrical connection paths and improving signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional multi-layer contact hole structures are used for gate electrical connection, then vertical electrical connection is achieved, but the connection path length increases leading to high resistance and capacitance delay
Solution Approach 1:
The patent transitions from a vertical multi-layer contact hole structure to a horizontal same-layer connection structure. The gate electrical connection pattern is formed on the same layer as the gate pattern, eliminating the need for vertical through-contact holes and reducing the electrical connection path length, thereby decreasing resistance and capacitance delay.
Solution Approach 2:
The patent extracts and eliminates the contact hole structure from the gate electrical connection path. By forming the gate electrical connection pattern directly on the same layer as the gate pattern without requiring contact holes to penetrate through multiple layers, the connection path is shortened and resistance is reduced.
2Reliability
If contact hole structures are used for inter-layer electrical connection, then vertical connection is established, but manufacturing complexity increases
Solution Approach 1:
The patent changes the connection dimension from vertical (through contact holes) to horizontal (same-layer pattern). The gate electrical connection pattern is formed on the same layer as the gate pattern, eliminating the need for complex multi-layer alignment and contact hole formation processes, thereby simplifying manufacturing.
3Adaptability or versatility
If long electrical connection paths are used, then connection flexibility is maintained, but power consumption increases due to high resistance
Solution Approach 1:
The patent removes the unnecessary contact hole structures from the electrical connection path, directly connecting the gate electrical connection pattern to the gate pattern on the same layer. This extraction of intermediate connection structures reduces the overall path length and resistance, thereby reducing power consumption.
Data Source
AI summary
The present disclosure provides a standard cell template and a semiconductor structure. The standard cell template includes a first well region and a second well region, arranged along a first direction; a first gate pattern, located in the first well region and extending along the first direction, for defining a first gate; a second gate pattern, located in the second well region and extending along the first direction, for defining a second gate; and a gate electrical connection pattern, located between the first gate pattern and the second gate pattern, for defining a gate electrical connection structure; where the gate electrical connection structure is arranged on the same layer as the first gate and the second gate to electrically connect the first gate and/or the second gate.