Standard Cell Differentiation via Graph Matching
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Solution Overview
Problem
The globalization of Integrated Circuit (IC) production leads to security concerns due to complex international supply chains, making it difficult to verify the authenticity of IC designs, especially with small node sizes and complex designs, where it's hard to detect modifications during manufacturing.
Innovation Solution
A scalable methodology for standard cell differentiation using graph-based topology and transistor attributes, incorporating graph isomorphism and exact/inexact matching criteria, which allows for 100% differentiation between cells by capturing all pertinent layers and attributes like transistor width or fin count, ensuring accurate cell identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional supply chain security methods (clearance and surveillance) are used, then security control is attempted, but they are ineffective against complex international supply chains and cannot detect design modifications during manufacturing
Solution Approach 1:
The patent applies preliminary action by embedding unique identification features (watermarks, fingerprints, or other distinctive markers) into the IC design data before manufacturing. This allows the design to be traced and verified throughout the supply chain, enabling detection of unauthorized modifications without requiring complex surveillance of the entire manufacturing process.
Solution Approach 2:
The patent implements feedback mechanisms through verification systems that compare the manufactured IC's identification features against the original design data. This feedback loop enables continuous monitoring and verification of design fidelity throughout the supply chain, allowing security personnel to detect and respond to modifications.
2Productivity
If small node sizes and complex designs are used, then IC functionality and performance are improved, but it becomes difficult to detect whether the design was faithfully reproduced or modified during manufacturing
Solution Approach 1:
The patent introduces intermediary elements (identification features, watermarks, or distinctive markers) that are embedded within the IC design. These intermediaries serve as detectable signals that do not interfere with the functional performance of the small-node IC design but enable verification of design fidelity throughout manufacturing and supply chain processes.
3Measurement precision
If comprehensive verification of all IC layers and attributes is performed, then cell differentiation accuracy is improved, but processing time and computational resources increase
Solution Approach 1:
The patent extracts and focuses verification efforts on specific critical layers and identification features rather than analyzing every layer and attribute of the IC design. By identifying and prioritizing the most discriminating features for cell differentiation, the system achieves high accuracy while reducing computational overhead and processing time.
Data Source
AI summary
In an approach to standard cell differentiation using topology and transistor attributes, a first circuit representation of an unidentified cell is received. The first circuit representation of the unidentified cell is converted to a first graph. A second circuit representation of each of one or more golden reference cells are retrieved. The second circuit representation of each of the one or more golden reference cells are converted to one or more second graphs. The first graph is matched to each of the one or more second graphs. One or more match results are reported based on the matching of the first graph to each of the one or more second graphs.